---
title: "ISA bus protocols"
subject: "Embedded System"
chapter: 5
key: "semester_6/embedded_system:isa-bus-protocols"
source: https://www.bctengineer.com/q/semester_6/embedded_system/isa-bus-protocols
site: BCT Engineering
---

# ISA bus protocols

Embedded System · Chapter 5: Interfacing

- Asked in: 2078 Baisakh, 3 marks
- Video: [Embedded System : ISA Bus | Niranjana A R](https://www.youtube.com/watch?v=y3W_Dk9xMgU) — S6 ECE
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/embedded_system/isa-bus-protocols
- Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-5

## Question

Describe the ISA bus protocols.

## Short answer

The ISA bus protocol is a synchronous compromise strobe/handshake: a fixed-cycle transfer (default 4 cycles) can be extended by the device pulling I/O CH RDY low. The master places address, asserts MEMR/W or IOR/W, and the slave responds; DMA and IRQ lines support block transfers and interrupts.

## Answer

The **ISA (Industry Standard Architecture) bus** is the 8/16-bit expansion bus of the IBM PC/AT, used with 80x86 processors and clocked at about 8 MHz. It is a synchronous bus with separate address, data and control lines. It uses a **compromise strobe/handshake** protocol: a transfer normally finishes in a fixed number of clock cycles (like a strobe), but a slow device can stretch it by pulling the ready line low (like a handshake). The processor (or a DMA controller) is the bus master and a card responds as slave.

**Main signals:**
- Address lines: SA0-SA19 (and LA17-LA23 for 16 MB), data lines SD0-SD15.
- Control: **MEMR, MEMW** (memory read/write), **IOR, IOW** (I/O read/write), **ALE/BALE** (address latch enable).
- **I/O CH RDY (CHRDY)** (ready line to insert wait states), **IRQ** lines (interrupts), **DRQ/DACK** (DMA request and acknowledge), RESET, CLK.

**Read cycle (memory or I/O):**
1. Cycle C1: the master puts the address on the address lines and asserts ALE/BALE to latch it.
2. Cycle C2: the master asserts MEMR (or IOR) to tell the addressed device to put data on the data bus.
3. Cycle C3: the device places the data on the bus. If the device is slow, it pulls CHRDY low to insert **wait states** until the data is ready.
4. Cycle C4: the master reads the data and deactivates MEMR/IOR; the cycle ends. A default cycle therefore takes 4 clock cycles, plus any wait states.

**Write cycle:** the same, but the master puts data on the data lines and asserts MEMW or IOW; the device latches the data, again using CHRDY to add wait states if needed.

**DMA:** a device raises DRQ; the DMA controller replies with DACK, becomes the master and generates the memory and I/O read/write signals.

**Interrupt:** a card asserts an IRQ line to the interrupt controller.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What is the ISA bus?
   A. The 8/16-bit expansion bus of the IBM PC/AT, about 8 MHz, with processor or DMA as master
   B. A serial bus with two wires
   C. A wireless protocol
   D. A 64-bit synchronous bus at GHz speeds
   Answer: A. The master drives address and control; the card responds as slave. (Key point: ISA bus basics)

2. How does a slow ISA device insert wait states?
   A. By asserting MEMW
   B. By raising ALE
   C. By pulling RESET
   D. By lowering I/O CH RDY
   Answer: D. I/O CH RDY is the ready line used for wait states. (Key point: Wait states)

3. In an ISA read cycle, what does the master do?
   A. Puts the address (latched by BALE/ALE), asserts MEMR or IOR, then reads the data
   B. Asserts MEMW and places data
   C. Sends IRQ
   D. Waits for DACK
   Answer: A. The read strobe tells the device to place data on the bus. (Key point: Read cycle)

4. How does DMA work on the ISA bus?
   A. The DMA uses wait states only
   B. A device raises DRQ, the DMA controller sends DACK and becomes master
   C. The device sends IRQ2
   D. The CPU raises DACK
   Answer: B. The DMA controller then generates memory and I/O read/write signals. (Key point: ISA DMA)

## Related in other subjects

- [ISA bus signals; replacement by PCI bus](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aisa-pci-bus) — Instrumentation II, chapter 2
- [Short introduction to ISA bus](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aisa-bus) — Instrumentation II, chapter 2