---
title: "Pipelining and multi-stage pipeline"
subject: "Embedded System"
chapter: 2
key: "semester_6/embedded_system:pipelining-stages"
source: https://www.bctengineer.com/q/semester_6/embedded_system/pipelining-stages
site: BCT Engineering
---

# Pipelining and multi-stage pipeline

Embedded System · Chapter 2: Hardware Design Issues

- Asked in: 2076 Baisakh, 4 marks; 2078 Chaitra; 2075 Baisakh, 4 marks (asked 3 times)
- Video: [Instruction Pipeline Architecture](https://www.youtube.com/watch?v=YhGv5AOcz1s) — TutorialsPoint
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/embedded_system/pipelining-stages
- Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-2

## Question

What do you mean by pipelining? Explain (with a diagram) the stages of a pipeline, e.g. 5-stage or 6-stage pipelining.

## Short answer

Pipelining overlaps instruction execution by splitting it into stages like IF (fetch), ID (decode), EX (execute), MEM (memory), WB (write back). This increases throughput, ideally one instruction per cycle, though latency remains unchanged. Hazards are managed with forwarding and stalls.

## Answer

**Pipelining** is a technique that overlaps the execution of several instructions by splitting instruction processing into stages, each handled by separate hardware. Like an assembly line, a new instruction enters the pipeline every clock cycle, so throughput increases (ideally one instruction per cycle) even though the latency of a single instruction does not fall.

#### Stages of a 5-stage pipeline
1. **IF - Instruction Fetch:** read the instruction from memory at PC; PC <- PC + 1.
2. **ID - Instruction Decode:** decode the opcode and read the register operands.
3. **EX - Execute:** the ALU performs the operation or computes the address.
4. **MEM - Memory access:** read or write data memory (load/store).
5. **WB - Write Back:** write the result to the register file.

(The standard 6-stage pipeline uses: **FI** fetch instruction, **DI** decode instruction, **CO** calculate operand (effective) address, **FO** fetch operands, **EI** execute instruction, **WO** write operand/result.)

#### Timing diagram
```text
 Cycle:   1   2   3   4   5   6   7   8
 Inst 1:  IF  ID  EX  MEM WB
 Inst 2:      IF  ID  EX  MEM WB
 Inst 3:          IF  ID  EX  MEM WB
 Inst 4:              IF  ID  EX  MEM WB
```
Without pipelining, 4 instructions need 20 cycles; with the pipeline they need 8 (k + n − 1 = 5 + 4 − 1).

Hazards (structural, data, control/branch) can stall the pipeline; they are handled by forwarding, stalls and branch prediction.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What is pipelining?
   A. Removing the ALU
   B. Executing one instruction at a time
   C. Doubling the clock
   D. Overlapping execution of several instructions by splitting processing into stages
   Answer: D. Like an assembly line, a new instruction enters each cycle, raising throughput. (Key point: Pipelining definition)

2. Does pipelining reduce the latency of a single instruction?
   A. No, throughput rises but single-instruction latency does not fall
   B. Yes, by 5 times
   C. Yes, to zero
   D. It increases throughput only for branches
   Answer: A. Each instruction still passes through every stage. (Key point: Latency effect)

3. Which is the correct 5-stage order?
   A. ID, IF, MEM, EX, WB
   B. IF, ID, EX, MEM, WB
   C. EX, IF, ID, WB, MEM
   D. WB, MEM, EX, ID, IF
   Answer: B. Fetch, decode, execute, memory access, write back. (Key point: Five stages)

4. How many cycles for 4 instructions in a 5-stage pipeline (no stalls)?
   A. 5
   B. 20
   C. 8
   D. 9
   Answer: C. k + n - 1 = 5 + 4 - 1 = 8 cycles versus 20 unpipelined. (Key point: Cycle count)

5. How are pipeline hazards handled?
   A. Increasing the word length
   B. Removing the clock
   C. Deleting instructions
   D. Forwarding, stalls and branch prediction
   Answer: D. Structural, data and control hazards are handled by forwarding, stalls and branch prediction. (Key point: Hazards)

## Related in other subjects

- [Six stage pipeline technique](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Asix-stage-pipeline) — Microprocessor, chapter 6
- [Six-stage instruction pipeline](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Asix-stage-pipeline) — Computer Organization and Architecture, chapter 4
- [Four-segment instruction pipeline and space-time diagram](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Afour-segment-pipeline) — Computer Organization and Architecture, chapter 4, asked 5×
- [Crosspoints in three-stage switch (4 inputs, 5 arrays)](https://www.bctengineer.com/question.md?key=semester_8%2Ftelecommunications%3Acrosspoints-4-input-5-second) — Telecommunications, chapter 4, asked 2×