--- title: "Top-down view for F = xz + yz'" subject: "Embedded System" chapter: 8 key: "semester_6/embedded_system:positive-photoresist-topdown-xz-yzbar" source: https://www.bctengineer.com/q/semester_6/embedded_system/positive-photoresist-topdown-xz-yzbar site: BCT Engineering --- # Top-down view for F = xz + yz' Embedded System · Chapter 8: IC Technology - Asked in: 2075 Bhadra, 5+3 marks - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_6/embedded_system/positive-photoresist-topdown-xz-yzbar - Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-8 ## Question Draw a top down view and schematic for the following function: F = xz + yz'. Describe with suitable diagram about positive photoresist used in photolithography. ## Short answer F = xz + yz’ is built as F = NOT(G) where G = NOT(xz+yz’); pull-down: (x series z) || (y series z’), pull-up: (x||z) series (y||z’), 12 transistors. Positive photoresist dissolves where UV-exposed, so the developed pattern matches the mask clear areas; it provides high resolution. ## Answer #### Schematic and top-down view of F = xz + yz' Static CMOS gates are inverting, so F is made as F = NOT(G), where G = NOT(xz + yz'). One inverter produces z' and another produces F from G. ```text Pull-up (PMOS) Pull-down (NMOS) VDD G | +----+----+ (x || z) | | | x y (y || z') | | | z z' G | | +----+----+ | GND z --[INV]-- z' G --[INV]-- F ``` Pull-down: (x in series with z) in parallel with (y in series with z'). Pull-up (the dual): (x parallel z) in series with (y parallel z'). In all, 12 transistors (inverter for z' = 2, gate = 8, output inverter = 2). Simplified top-down (stick) view of the gate part: ```text VDD =============================== metal | | | | +-+---+-----+---+-+ p+ diffusion | x z y z' | poly gates run | | | | | | vertically +-+---+-----+---+-+ across both rows |_______ G _______ metal output +-+---+-----+---+-+ n+ diffusion | | | | GND =============================== metal ``` Legend: the vertical poly lines x, z, y, z' cross the p+ row (top) and the n+ row (bottom); each crossing is a transistor. Metal joins the drain areas to the output G. #### Positive photoresist A positive photoresist is a light-sensitive polymer that becomes **soluble in the developer where it has been exposed to UV light**. The unexposed part remains and protects the layer below. ```text Exposure (UV through mask) After development UV UV UV UV _____ _____ [####] [####] mask |resist| |resist| ===resist=========== ===SiO2============ ======SiO2========== gap = window opened ======Si wafer======= ``` - The pattern on the wafer is the **same as the mask** (clear areas of the mask become openings). - Advantages: better resolution, easier to remove, widely used for fine features. - Example: Novolac resin with diazonaphthoquinone (DNQ) sensitiser. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What happens to a positive photoresist where it is exposed to UV light? A. It becomes soluble in the developer and is washed away B. It hardens and stays C. It turns into SiO2 D. It becomes a conductor Answer: A. Exposed positive resist becomes soluble in developer; the unexposed part remains as protection. (Key point: Positive resist behaviour) 2. With a positive photoresist, how does the pattern on the wafer relate to the mask? A. It is the inverse of the mask B. It is the same as the mask, clear areas becoming openings C. It is unrelated to the mask D. It is mirrored and enlarged 5x Answer: B. Clear mask areas expose the resist, which dissolves, giving openings that match the mask. (Key point: Pattern polarity) 3. Why is F = xz + yz' built as NOT(G) with G = NOT(xz + yz')? A. PMOS transistors cannot be used in the pull-up B. Static CMOS gates are inverting, so an extra output inverter restores the function C. It reduces the transistor count to 8 D. z' is not needed then Answer: B. A single static CMOS stage gives only an inverted function, so G is made first and then inverted. (Key point: Inverting CMOS gate) 4. What is the pull-down network for G = NOT(xz + yz')? A. (x parallel z) in series with (y parallel z') B. All four transistors in series C. (x series z) in parallel with (y series z') D. All four transistors in parallel Answer: C. AND terms become series chains in the NMOS network, ORed terms are in parallel. The pull-up is the dual. (Key point: Pull-down/pull-up structure) ## Related in Embedded System - [IC manufacturing steps; top-down F = xz + y](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aic-manufacturing-steps-topdown-xz-y) — Embedded System, chapter 8 - [Photolithography importance; BJT structure](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aphotolithography-bjt-structure) — Embedded System, chapter 8 ## Related in other subjects - [Schematic diagram of rural gravity scheme](https://www.bctengineer.com/question.md?key=semester_5%2Fwater_supply_engineering%3Arural-gravity-scheme-diagram) — Water Supply Engineering, chapter 1, asked 5× - [Top-down approach](https://www.bctengineer.com/question.md?key=semester_5%2Fsoftware_engineering%3Atop-down-approach) — Software Engineering, chapter 3 - [Top-down integration problems; regression testing](https://www.bctengineer.com/question.md?key=semester_5%2Fsoftware_engineering%3Atop-down-integration-regression) — Software Engineering, chapter 8 - [Positive edge SR flip-flop and its state diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-positive-edge-state-diagram) — Digital Logic, chapter 6