---
title: "Design ROM for A,B,C to F1-F4 table"
subject: "Embedded System"
chapter: 4
key: "semester_6/embedded_system:rom-design-abc-f1-f4"
source: https://www.bctengineer.com/q/semester_6/embedded_system/rom-design-abc-f1-f4
site: BCT Engineering
---

# Design ROM for A,B,C to F1-F4 table

Embedded System · Chapter 4: Memory

- Asked in: 2078 Poush, 5 marks
- Video: [PROM (Programmable Read Only Memory) || Implementing Boolean Functions using PROM || PROM Example](https://www.youtube.com/watch?v=5rcdQahTZh8) — Sudhakar Atchala
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/embedded_system/rom-design-abc-f1-f4
- Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-4

## Question

Design a ROM to store the following information:

| A | B | C | F1 | F2 | F3 | F4 |
|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 1 | 1 | 1 |
| 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 0 | 1 | 0 |
| 1 | 0 | 1 | 1 | 1 | 1 | 1 |
| 1 | 1 | 0 | 1 | 0 | 0 | 0 |
| 1 | 1 | 1 | 0 | 0 | 1 | 1 |

## Short answer

8x4 ROM with 3-to-8 decoder. F1 = w4+w5+w6, F2 = w0+w2+w5, F3 = w0+w1+w2+w4+w5+w7, F4 = w0+w1+w5+w7.

## Answer

The table has 3 address inputs, so there are 2^3 = 8 words, each 4 bits wide. The ROM is therefore **8 x 4**.

#### Stored contents
| Address (A,B,C) | Word (F1,F2,F3,F4) |
|---|---|
| 000 (word line 0) | 0111 |
| 001 (word line 1) | 0011 |
| 010 (word line 2) | 0110 |
| 011 (word line 3) | 0000 |
| 100 (word line 4) | 1010 |
| 101 (word line 5) | 1111 |
| 110 (word line 6) | 1000 |
| 111 (word line 7) | 0011 |

#### Design
Use a 3-to-8 decoder (address lines select exactly one word line) and one OR gate per output bit. Connect a word line to an OR gate only where that word stores a 1 in the column (a programmable connection/transistor at the crosspoint).

| Output | Word lines ORed (addresses with a 1) | Output expression |
|---|---|---|
| F1 | 4, 5, 6 | F1 = w4 + w5 + w6 |
| F2 | 0, 2, 5 | F2 = w0 + w2 + w5 |
| F3 | 0, 1, 2, 4, 5, 7 | F3 = w0 + w1 + w2 + w4 + w5 + w7 |
| F4 | 0, 1, 5, 7 | F4 = w0 + w1 + w5 + w7 |

```text
  A B C (address)
   |  |  |    +----------+ w0..w7  OR gates
   +--+--+--->| 3-to-8  |==> word lines ==> [ OR ]--> F1
              | decoder  |                  [ OR ]--> F2
              +----------+                  ...   --> F4
```

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. The table has 3 inputs (A,B,C) and 4 outputs. What size is the ROM?
   A. 8 x 4
   B. 4 x 8
   C. 3 x 4
   D. 16 x 4
   Answer: A. 2^3 = 8 words, each 4 bits wide: 8 x 4. (Key point: ROM size)

2. Which decoder is used?
   A. 3-to-8
   B. 2-to-4
   C. 4-to-16
   D. 1-to-2
   Answer: A. 3 address lines select one of 8 word lines. (Key point: Decoder)

3. F1 is 1 for addresses 100, 101 and 110. Which expression is correct?
   A. w4 + w5 + w6
   B. w0 + w1 + w2
   C. w4 + w5 + w7
   D. w1 + w3 + w5
   Answer: A. Binary 100, 101, 110 are word lines 4, 5, 6. (Key point: F1 expression)

4. Where is a word line connected to an OR gate?
   A. Only where the stored bit in that column is 1
   B. Wherever the bit is 0
   C. Everywhere
   D. Only to F1
   Answer: A. Crosspoint connections are made where a 1 is stored; left open for 0. (Key point: OR connections)

## Close variants set in other exams

- [Design ROM for X,Y,Z to F1-F4 table](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Arom-design-xyz-f1-f4) — Embedded System, chapter 4, asked 2×

## Related in Embedded System

- [Design ROM for X,Y,Z to F1,F2 table](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Arom-design-xyz-f1-f2) — Embedded System, chapter 4

## Related in other subjects

- [Find F1 and F2 for equilibrium](https://www.bctengineer.com/question.md?key=semester_1%2Fapplied_mechanics%3Aunknown-forces-f1-f2-equilibrium) — Applied Mechanics, chapter 2
- [PLA for F1 = Σm(3,5,6,7), F2 = Σm(0,2,4,7)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Apla-two-functions) — Digital Logic, chapter 4