---
title: "Design ROM for X,Y,Z to F1,F2 table"
subject: "Embedded System"
chapter: 4
key: "semester_6/embedded_system:rom-design-xyz-f1-f2"
source: https://www.bctengineer.com/q/semester_6/embedded_system/rom-design-xyz-f1-f2
site: BCT Engineering
---

# Design ROM for X,Y,Z to F1,F2 table

Embedded System · Chapter 4: Memory

- Asked in: 2070 Magh, 5 marks
- Video: [PROM (Programmable Read Only Memory) || Implementing Boolean Functions using PROM || PROM Example](https://www.youtube.com/watch?v=5rcdQahTZh8) — Sudhakar Atchala
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/embedded_system/rom-design-xyz-f1-f2
- Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-4

## Question

Design a ROM that will store the following words in the corresponding addresses.

| X | Y | Z | F1 | F2 |
|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 0 | 1 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 0 | 0 |
| 1 | 0 | 1 | 1 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 0 |

## Short answer

8x2 ROM with 3-to-8 decoder. F1 = w0+w1+w5+w7, F2 = w2+w3+w5+w6.

## Answer

The table has 3 address inputs, so there are 2^3 = 8 words, each 2 bits wide. The ROM is therefore **8 x 2**.

#### Stored contents
| Address (X,Y,Z) | Word (F1,F2) |
|---|---|
| 000 (word line 0) | 10 |
| 001 (word line 1) | 10 |
| 010 (word line 2) | 01 |
| 011 (word line 3) | 01 |
| 100 (word line 4) | 00 |
| 101 (word line 5) | 11 |
| 110 (word line 6) | 01 |
| 111 (word line 7) | 10 |

#### Design
Use a 3-to-8 decoder (the address lines select exactly one word line) and one OR gate per output bit. Connect a word line to an OR gate only where that word stores a 1 in that column (a programmable connection at the crosspoint).

| Output | Word lines ORed (addresses with a 1) | Output expression |
|---|---|---|
| F1 | 0, 1, 5, 7 | F1 = w0 + w1 + w5 + w7 |
| F2 | 2, 3, 5, 6 | F2 = w2 + w3 + w5 + w6 |

```text
 X,Y,Z (address)
    |    +-----------+  w0..w7
    +--->|  3-to-8   |===> word lines ===> [OR] --> F1
         |  decoder  |                     [OR] --> F2
         +-----------+
```
Each OR input is connected (by a transistor/fuse) to a word line only when that bit of the word is 1; the connection is left open for 0. When an address is applied, the decoder raises one word line and the OR gates output the stored word.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What is the size of the ROM for 3 address inputs and outputs F1, F2?
   A. 8 x 2
   B. 2 x 8
   C. 8 x 3
   D. 4 x 2
   Answer: A. 2^3 = 8 words of 2 bits. (Key point: ROM size)

2. F1 is 1 at XYZ = 000, 001, 101, 111. Which expression is correct?
   A. w0 + w1 + w5 + w7
   B. w2 + w3 + w5 + w6
   C. w0 + w1 + w4 + w7
   D. w1 + w3 + w5 + w7
   Answer: A. Those addresses are word lines 0, 1, 5, 7. (Key point: F1 expression)

3. What word (F1F2) is stored at address 101?
   A. 11
   B. 10
   C. 01
   D. 00
   Answer: A. At XYZ = 101 both F1 and F2 are 1. (Key point: Word at 101)

4. How many OR gates are needed?
   A. 2, one per output
   B. 8, one per word
   C. 3, one per address line
   D. 1
   Answer: A. One OR gate per output bit; here 2. (Key point: Number of OR gates)

## Related in Embedded System

- [Design ROM for A,B,C to F1-F4 table](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Arom-design-abc-f1-f4) — Embedded System, chapter 4, asked 2×
- [Design ROM for X,Y,Z to F1-F4 table](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Arom-design-xyz-f1-f4) — Embedded System, chapter 4, asked 2×

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