---
title: "Design ROM for X,Y,Z to F1-F4 table"
subject: "Embedded System"
chapter: 4
key: "semester_6/embedded_system:rom-design-xyz-f1-f4"
source: https://www.bctengineer.com/q/semester_6/embedded_system/rom-design-xyz-f1-f4
site: BCT Engineering
---

# Design ROM for X,Y,Z to F1-F4 table

Embedded System · Chapter 4: Memory

- Asked in: 2075 Bhadra, 5 marks
- Video: [PROM (Programmable Read Only Memory) || Implementing Boolean Functions using PROM || PROM Example](https://www.youtube.com/watch?v=5rcdQahTZh8) — Sudhakar Atchala
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/embedded_system/rom-design-xyz-f1-f4
- Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-4

## Question

Design a ROM to store the following information:

| X | Y | Z | F1 | F2 | F3 | F4 |
|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 1 | 0 |
| 0 | 0 | 1 | 1 | 1 | 0 | 0 |
| 0 | 1 | 0 | 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 1 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 | 0 | 1 | 1 |
| 1 | 0 | 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 | 1 | 1 |

## Short answer

8x4 ROM with 3-to-8 decoder. F1 = w1+w3+w6, F2 = w1+w2+w3+w5, F3 = w0+w3+w4+w6+w7, F4 = w2+w3+w4+w5+w7.

## Answer

The table has 3 address inputs, so there are 2^3 = 8 words, each 4 bits wide. The ROM is therefore **8 x 4**.

#### Stored contents
| Address (X,Y,Z) | Word (F1,F2,F3,F4) |
|---|---|
| 000 (word line 0) | 0010 |
| 001 (word line 1) | 1100 |
| 010 (word line 2) | 0101 |
| 011 (word line 3) | 1111 |
| 100 (word line 4) | 0011 |
| 101 (word line 5) | 0101 |
| 110 (word line 6) | 1010 |
| 111 (word line 7) | 0011 |

#### Design
Use a 3-to-8 decoder (the address lines select exactly one word line) and one OR gate per output bit. Connect a word line to an OR gate only where that word stores a 1 in that column (a programmable connection at the crosspoint).

| Output | Word lines ORed (addresses with a 1) | Output expression |
|---|---|---|
| F1 | 1, 3, 6 | F1 = w1 + w3 + w6 |
| F2 | 1, 2, 3, 5 | F2 = w1 + w2 + w3 + w5 |
| F3 | 0, 3, 4, 6, 7 | F3 = w0 + w3 + w4 + w6 + w7 |
| F4 | 2, 3, 4, 5, 7 | F4 = w2 + w3 + w4 + w5 + w7 |

```text
 X,Y,Z (address)
    |    +-----------+  w0..w7
    +--->| 3-to-8   |===> word lines ===> [OR] --> F1
         | decoder   |                      [OR] --> F2
         +-----------+                      ...
```
Each OR input is connected (by a transistor/fuse) to a word line only when that bit of the word is 1; the connection is left open for 0. When an address is applied, the decoder raises one word line and the OR gates output the stored word.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What size ROM stores this table (3 inputs X,Y,Z; outputs F1-F4)?
   A. 8 x 4
   B. 4 x 8
   C. 8 x 3
   D. 16 x 4
   Answer: A. 3 address lines give 8 words of 4 bits. (Key point: ROM size)

2. What word is stored at address 001 (F1F2F3F4)?
   A. 1100
   B. 0010
   C. 0101
   D. 1111
   Answer: A. At XYZ=001, F1=1, F2=1, F3=0, F4=0 giving 1100. (Key point: Word at 001)

3. F1 is 1 at XYZ = 001, 011, 110. Which expression is correct?
   A. w1 + w3 + w6
   B. w0 + w3 + w4
   C. w2 + w3 + w5
   D. w1 + w2 + w6
   Answer: A. Those addresses are word lines 1, 3 and 6. (Key point: F1 expression)

4. What does the 3-to-8 decoder do when an address is applied?
   A. Raises exactly one word line
   B. Raises all word lines
   C. Outputs the data directly
   D. Blows fuses
   Answer: A. One word line is raised and the OR gates output the stored word. (Key point: Use of the decoder)

## Close variants set in other exams

- [Design ROM for A,B,C to F1-F4 table](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Arom-design-abc-f1-f4) — Embedded System, chapter 4, asked 2×

## Related in Embedded System

- [Design ROM for X,Y,Z to F1,F2 table](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Arom-design-xyz-f1-f2) — Embedded System, chapter 4

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