---
title: "Largest of four integers processor"
subject: "Embedded System"
chapter: 2
key: "semester_6/embedded_system:spp-largest-of-four"
source: https://www.bctengineer.com/q/semester_6/embedded_system/spp-largest-of-four
site: BCT Engineering
---

# Largest of four integers processor

Embedded System · Chapter 2: Hardware Design Issues

- Asked in: 2073 Bhadra, 8 marks
- Video: [Designing Single Purpose Processor To Calculate GCD (HCF).](https://www.youtube.com/watch?v=Wy344fMRnOo) — AFlick
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/embedded_system/spp-largest-of-four
- Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-2

## Question

Develop algorithm; draw the state diagram and design the datapath of a custom single purpose processor that determines the largest of four integers. Propose the block diagram of its controller also.

## Short answer

The algorithm initializes max = a, then sequentially compares b, c, d, updating max if larger. The datapath uses a 4:1 mux, comparator, and max register; the controller is a 6-state FSM with inputs start and gt, outputs sel, load, out_en.

## Answer

**Assumption:** four 8-bit integers a, b, c, d are available on input ports; the processor outputs the largest value when *start* is given.

#### Algorithm
```text
 max = a
 if (b > max) max = b
 if (c > max) max = c
 if (d > max) max = d
 output max
```

#### State diagram (FSMD)
```text
 S0 --start--> S1 (MAX=a) --> S2 (if b>MAX: MAX=b)
   ^                                  |
   |                                  v
 S5 (out=MAX, done) <-- S4 (if d>MAX: MAX=d) <-- S3 (if c>MAX: MAX=c)
```

| State | Actions | Condition / next |
|---|---|---|
| S0 wait | done = 0 | start = 0: stay in S0; start = 1: S1 |
| S1 | MAX = a | S2 |
| S2 | if gt then MAX = b | S3 |
| S3 | if gt then MAX = c | S4 |
| S4 | if gt then MAX = d | S5 |
| S5 | out = MAX, done = 1 | S0 |

(gt = comparator output "selected input > MAX".)

#### Datapath
```text
  a --+
  b --+--> [4:1 mux] --+--> [ > comparator ] --> gt
  c --+     (sel 2b)   |            ^
  d --+                |            |
                       v            |
                   [ MAX register ]-+
                       |
                       v
                      out
```
Components: a 4:1 multiplexer selecting the input (sel = 00 a, 01 b, 10 c, 11 d), an 8-bit comparator (selected input > MAX), an 8-bit register MAX with load enable (load = gt, or unconditional in S1), and an output buffer. Control signals: sel[1:0], load, out_en.

#### Controller block diagram
```text
 start, status flags --> +-------------+   +-----------+
 (from datapath)         | Next-state  |-->| State     |
                         | logic       |   | register  |
                         +------^------+   +-----+-----+
                                |   current state |
                                +-----------------+
                                                  v
                                           +-------------+
                                           | Output logic|--> control
                                           +-------------+    signals
```

6 states, 3-bit state register. Output logic: S1: sel = 00, ld = 1; S2: sel = 01, ld = gt; S3: sel = 10, ld = gt; S4: sel = 11, ld = gt; S5: out_en = 1, done = 1. The controller's inputs are *start* and the status signal *gt* from the datapath.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What is the basic algorithm for largest of four?
   A. Sort all four numbers fully
   B. Set max = a, then compare b, c, d in turn and update max if larger
   C. Add the four numbers and divide by 4
   D. Compare a with d only
   Answer: B. A running maximum is updated whenever the next input exceeds it. (Key point: Algorithm)

2. When is MAX loaded in states S2-S4?
   A. Always
   B. Only when start = 1
   C. Only when gt (selected input > MAX) is true
   D. Only when done = 1
   Answer: C. The comparator output gt controls the load enable of the MAX register. (Key point: Load condition)

3. What is the 4:1 multiplexer for?
   A. Selecting the output buffer
   B. Selecting the state
   C. Counting the inputs
   D. Selecting which of a, b, c, d goes to the comparator and register
   Answer: D. A 2-bit select (00 a, 01 b, 10 c, 11 d) feeds one input at a time to the comparator. (Key point: Datapath multiplexer)

4. How many states does the controller have, and how wide is the state register?
   A. 6 states, 3 bits
   B. 4 states, 2 bits
   C. 5 states, 3 bits
   D. 6 states, 6 bits
   Answer: A. S0-S5 are six states, so a 3-bit binary state register is needed. (Key point: State count)

## Related in Embedded System

- [Single-purpose processor for power](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aspp-power) — Embedded System, chapter 2, asked 2×
- [Fibonacci single-purpose processor](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aspp-fibonacci) — Embedded System, chapter 2, asked 2×
- [Factorial single-purpose processor](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aspp-factorial) — Embedded System, chapter 2
- [Design LCM single-purpose processor](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aspp-lcm-datapath-controller) — Embedded System, chapter 2
- [Prime number checking processor](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aspp-prime-check) — Embedded System, chapter 2
- [GPP operation: datapath and controller](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Agpp-datapath-controller) — Embedded System, chapter 2, asked 4×

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