--- title: "Optimization of single-purpose processors" subject: "Embedded System" chapter: 2 key: "semester_6/embedded_system:spp-optimization" source: https://www.bctengineer.com/q/semester_6/embedded_system/spp-optimization site: BCT Engineering --- # Optimization of single-purpose processors Embedded System · Chapter 2: Hardware Design Issues - Asked in: 2070 Bhadra, 8 marks; 2071 Bhadra, 8 marks; 2072 Magh, 8 marks; 2075 Bhadra, 4+4 marks; 2079 Jestha, 2+6 marks; 2079 Asoj, 8 marks (asked 6 times) - Video: [Single purpose processor|Custom single purpose processor|Optimization of single purpose processor](https://www.youtube.com/watch?v=hYse_pq3UmM) — Last Night Study - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_6/embedded_system/spp-optimization - Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-2 ## Question What is optimization? Explain in detail the optimization (opportunities and parameters) of a custom single-purpose processor with a suitable example. ## Short answer Optimization improves design metrics by trade-offs. For a custom SPP, opportunities exist at algorithm, FSMD (merging states), datapath (unit sharing, bit-width reduction), and FSM controller (state encoding) levels. Example: merging states in an array-sum FSMD reduces cycles but may increase hardware size. ## Answer **Optimization** is the process of improving the design metrics (performance, size, power, cost) of a system by making design trade-offs, since the metrics compete. For a custom single-purpose processor (SPP), optimisation is done at four levels, each with its own opportunities and parameters. #### 1. Optimising the original program (algorithm) - Choose a faster algorithm (e.g. GCD by Euclid's subtraction/modulo method instead of trial division). - Reduce operations: replace multiplication by shifts, remove redundant computation, and pick smaller data types (bit widths). #### 2. Optimising the FSMD - **Scheduling:** merge states so that independent operations run in the same state (more parallelism, fewer clock cycles). - **Removing unnecessary states:** e.g. a wait state or a separate state for a trivial assignment. - **Parameters:** number of states, clock cycles per task, clock period. #### 3. Optimising the datapath - **Share functional units** (one ALU used in different states) to reduce size, at the cost of extra muxes and more states. - **Use multi-functional units**, remove unused registers, and **reduce bit widths**. - **Parameters:** number of registers/ALUs, multiplexer count, critical path (clock period). #### 4. Optimising the FSM (controller) - **State encoding:** binary (fewest flip-flops, more logic) versus one-hot (more flip-flops, faster logic). - **State minimisation:** merge equivalent states. - **Parameters:** flip-flops, gates, delay. #### Example: summing the elements of an array in a loop ```text Original FSMD: Optimised FSMD: S1: i = 0 S1: i = 0, s = 0 S2: s = 0 S2: if i 2 states, fewer cycles) S4: s = s+a[i] S5: i = i+1 ``` Merging S1/S2 and S3/S4/S5 reduces the cycle count (performance up) but needs two independent adders working in the same state (size up). Sharing a single adder instead would reduce size but cost extra cycles. The designer therefore picks the point that best satisfies the constraints. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is optimisation in design? A. Maximising every metric simultaneously B. Improving design metrics by making trade-offs because metrics compete C. Removing the processor D. Increasing NRE only Answer: B. Optimisation improves metrics such as performance, size, power and cost through trade-offs. (Key point: Definition of optimization) 2. At which four levels is an SPP optimised? A. Lens, sensor, ADC, DAC B. Cache, bus, OS, compiler C. Program, FSMD, datapath, FSM D. Hardware only Answer: C. Original program (algorithm), FSMD, datapath, and FSM controller. (Key point: Levels of optimisation) 3. What does merging states in the FSMD achieve? A. Larger program memory B. Fewer adders C. Lower clock rate D. Independent operations run in the same state, giving fewer clock cycles Answer: D. Scheduling more parallelism reduces cycles, improving performance, possibly at the cost of more hardware. (Key point: FSMD scheduling) 4. What is the trade-off of sharing one functional unit across states? A. Smaller size but more muxes and more states/cycles B. Faster and larger C. No change D. Fewer registers and fewer cycles Answer: A. Sharing saves area but needs multiplexers and extra cycles. (Key point: Datapath sharing) 5. How do binary and one-hot encoding compare? A. Binary is faster with more flip-flops B. Binary uses fewest flip-flops but more logic; one-hot uses more flip-flops but faster logic C. They are identical D. One-hot uses fewest flip-flops Answer: B. One-hot trades flip-flops for simpler, faster next-state logic. (Key point: State encoding) ## Related in Embedded System - [Fibonacci single-purpose processor](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aspp-fibonacci) — Embedded System, chapter 2, asked 2× - [Single-purpose processor for power](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aspp-power) — Embedded System, chapter 2, asked 2× - [Factorial single-purpose processor](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aspp-factorial) — Embedded System, chapter 2 - [Design LCM single-purpose processor](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aspp-lcm-datapath-controller) — Embedded System, chapter 2 - [ASIP versus general purpose processor](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aasip-vs-gpp) — Embedded System, chapter 2 - [Dual-purpose processor: median and variance](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Adual-purpose-median-variance) — Embedded System, chapter 2 ## Related in other subjects - [Determining single phase IM equivalent circuit parameters](https://www.bctengineer.com/question.md?key=semester_5%2Felectric_machines_ii%3Aequivalent-circuit-parameter-tests) — Electric Machines II, chapter 3 - [Single tone FM parameters](https://www.bctengineer.com/question.md?key=semester_5%2Fdata_communication%3Afm-single-tone-numeric) — Data Communication, chapter 5 - [Real-time scheduling; two-processor numerical](https://www.bctengineer.com/question.md?key=semester_6%2Foperating_system%3Arealtime-two-processor-fcfs-sjf-priority-rr) — Operating System, chapter 2