---
title: "Super scalar versus VLIW architecture"
subject: "Embedded System"
chapter: 2
key: "semester_6/embedded_system:superscalar-vs-vliw"
source: https://www.bctengineer.com/q/semester_6/embedded_system/superscalar-vs-vliw
site: BCT Engineering
---

# Super scalar versus VLIW architecture

Embedded System · Chapter 2: Hardware Design Issues

- Asked in: 2079 Jestha, 3+5 marks
- Video: [Superscalar vs VLIW  | Computer Organization and Architecture Lectures in Hindi](https://www.youtube.com/watch?v=xf7uzF_51WY) — Last moment tuitions
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/embedded_system/superscalar-vs-vliw
- Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-2

## Question

Explain the concept of pipelining. Differentiate super scalar and VLIW architecture.

## Answer

#### Pipelining
**Pipelining** divides instruction execution into stages (fetch, decode, execute, memory access, write-back). A new instruction enters the first stage each clock while earlier ones occupy later stages, so several instructions are in progress together and throughput approaches one instruction per cycle.

```text
 Inst 1: IF ID EX MEM WB
 Inst 2:    IF ID EX MEM WB
 Inst 3:       IF ID EX MEM WB
```

#### Superscalar versus VLIW
Both issue several instructions per clock using multiple functional units (parallel pipelines); they differ in who finds the parallelism.

| Point | Superscalar | VLIW (Very Long Instruction Word) |
|---|---|---|
| Parallelism found by | Hardware at run time (dynamic scheduling) | Compiler at compile time (static scheduling) |
| Instruction format | Ordinary, variable instructions | One very long word (e.g. 128 bits) containing several operations |
| Hardware complexity | High (dependency checking, reorder, branch prediction) | Low (no scheduling logic) |
| Power and area | Higher | Lower |
| Compiler complexity | Simpler | Complex; must schedule well |
| Code size | Smaller | Larger (NOPs for unused slots) |
| Binary compatibility | Good across generations | Poor; recompilation needed |
| Examples | Pentium, ARM Cortex-A, PowerPC | TI TMS320C6x DSP, Itanium |

**Result:** superscalar suits general computing; VLIW suits embedded and DSP, where the program is known beforehand and power matters.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How does pipelining raise throughput?
   A. Each instruction finishes in a single stage
   B. Several instructions occupy different stages in the same clock
   C. Instructions are executed strictly one after another
   D. Stages are removed
   Answer: B. A new instruction enters the first stage each clock while earlier ones are in later stages. (Key point: Pipelining concept)

2. Who finds instruction-level parallelism in superscalar and VLIW?
   A. Superscalar: compiler; VLIW: hardware
   B. Both: the programmer by hand
   C. Superscalar: hardware at run time; VLIW: compiler at compile time
   D. Both: the operating system
   Answer: C. Superscalar uses dynamic scheduling in hardware; VLIW relies on static scheduling by the compiler. (Key point: Who finds parallelism)

3. Which is true about hardware complexity?
   A. VLIW needs more scheduling hardware
   B. Both need identical hardware
   C. Superscalar has the lower power and area
   D. Superscalar needs dependency checking and reordering; VLIW has no scheduling logic
   Answer: D. VLIW moves scheduling to the compiler, so its hardware is simpler, smaller and lower power. (Key point: Hardware complexity)

4. Which is a disadvantage of VLIW?
   A. Larger code size from NOPs and poor binary compatibility
   B. Complex run-time dependency hardware
   C. Higher power than superscalar
   D. Cannot issue multiple operations
   Answer: A. Unused slots are filled with NOPs and recompilation is needed for new generations. (Key point: VLIW drawbacks)

## Related in Embedded System

- [Open loop versus closed loop control](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aopen-vs-closed-loop) — Embedded System, chapter 7, asked 6×
- [RTOS versus general-purpose OS](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Artos-vs-gpos) — Embedded System, chapter 6, asked 4×
- [Process versus thread differences](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aprocess-vs-thread) — Embedded System, chapter 6, asked 4×
- [User-level versus kernel-level threads](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Auser-vs-kernel-threads) — Embedded System, chapter 6, asked 2×
- [Embedded versus non-embedded systems](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aembedded-vs-non-embedded) — Embedded System, chapter 1
- [Multiprocessing versus multitasking](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Amultiprocessing-vs-multitasking) — Embedded System, chapter 6

## Related in other subjects

- [Distributed object versus multiprocessor architecture](https://www.bctengineer.com/question.md?key=semester_5%2Fsoftware_engineering%3Adistributed-object-vs-multiprocessor) — Software Engineering, chapter 3
- [Vector processing and pipelining performance](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Avector-pipeline-performance) — Computer Organization and Architecture, chapter 4, asked 2×
- [Parallel processing and pipelining](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aparallel-processing) — Computer Organization and Architecture, chapter 4
- [Data dependency problem in pipelining](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adata-dependency) — Computer Organization and Architecture, chapter 4