---
title: "Two-level bus architecture"
subject: "Embedded System"
chapter: 5
key: "semester_6/embedded_system:two-level-bus-architecture"
source: https://www.bctengineer.com/q/semester_6/embedded_system/two-level-bus-architecture
site: BCT Engineering
---

# Two-level bus architecture

Embedded System · Chapter 5: Interfacing

- Asked in: 2074 Bhadra, 3 marks
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/embedded_system/two-level-bus-architecture
- Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-5

## Question

Describe two-level bus architecture in detail.

## Short answer

A two-level bu architecture splits the system into a fast processor-memory bus and a slower peripheral bus connected by a bridge. The processor, cache, and memory run on the high-speed bus, while peripherals attach to the low-speed bus; the bridge translates protocols and isolates traffic, allowing the processor bus to operate at full speed.

## Answer

In a **two-level (hierarchical) bus architecture**, the system uses two buses of different speed connected by a bridge, instead of one common bus.

```text
 +-----------+      +--------+     +----------+
 | Processor |      | Cache/ |     |  Memory  |
 +-----+-----+      | DMA    |     +----+-----+
       |            +---+----+          |
 ======+================+===============+==== Processor-memory bus (fast)
                        |
                    +---+----+
                    | Bridge |
                    +---+----+
 =======================+====================== Peripheral bus (slow)
      |          |            |          |
   +--+--+    +--+--+      +--+--+    +--+--+
   |UART |    | Disk|      |Timer|    | I/O |
   +-----+    +-----+      +-----+    +-----+
```
- **Level 1: processor-local (processor-memory) bus:** high speed, short, connects the processor, cache, memory and DMA.
- **Level 2: peripheral (I/O) bus:** slower and standard (such as ISA/PCI), connecting peripherals.
- **Bridge:** converts the protocols and speeds between the buses and isolates the high-speed bus from peripheral traffic.

**Advantages:** the processor and memory can run at full speed; peripheral traffic does not slow it; slow peripherals are cheap and standard, and different peripheral buses can be supported. **Disadvantage:** the bridge adds cost, delay and complexity.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What are the two buses in a two-level bus architecture?
   A. A serial bus and an interrupt bus
   B. A fast processor-memory bus and a slower peripheral bus joined by a bridge
   C. Two identical buses for redundancy
   D. Address bus and data bus
   Answer: B. Level 1 is the high-speed processor-memory bus, level 2 the slower peripheral bus, connected through a bridge. (Key point: Structure of two-level bus)

2. What does the bridge do?
   A. Decodes memory addresses only
   B. Generates the system clock
   C. Converts protocols and speeds and isolates the fast bus from peripheral traffic
   D. Stores data permanently
   Answer: C. The bridge matches protocols/speeds and keeps slow peripheral traffic off the fast bus. (Key point: Role of the bridge)

3. What is the main advantage and disadvantage?
   A. Fewer buses and cheaper; slower processor
   B. Simpler design; no standard peripherals
   C. Processor runs at full speed; bridge adds cost, delay and complexity
   D. More wires; faster peripherals
   Answer: C. Peripheral traffic does not slow the processor-memory path, but the bridge adds cost and delay. (Key point: Advantage and disadvantage)

## Related in other subjects

- [Fault level: four 25 MVA generators, bus reactor](https://www.bctengineer.com/question.md?key=semester_7%2Fpower_plant_equipment%3Afault-four-25mva-bus-reactor) — Power Plant Equipment, chapter 4
- [Fault level at end of two 200 km lines](https://www.bctengineer.com/question.md?key=semester_5%2Fpower_system_analysis_ii%3Afault-two-stations-132kv-200km) — Power System Analysis II, chapter 3, asked 2×
- [Fault level: two 40 MVA generators, 2 Ω feeder](https://www.bctengineer.com/question.md?key=semester_7%2Fpower_plant_equipment%3Afault-two-40mva-2-ohm-feeder) — Power Plant Equipment, chapter 4, asked 5×
- [Time to lower level in two-orifice tank](https://www.bctengineer.com/question.md?key=semester_3%2Ffluid_mechanics%3Atwo-orifice-tank-lowering-time) — Fluid Mechanics, chapter 6