--- title: "Interrupt-driven I/O with vectored interrupt" subject: "Embedded System" chapter: 5 key: "semester_6/embedded_system:vectored-interrupt-io-flow" source: https://www.bctengineer.com/q/semester_6/embedded_system/vectored-interrupt-io-flow site: BCT Engineering --- # Interrupt-driven I/O with vectored interrupt Embedded System · Chapter 5: Interfacing - Asked in: 2071 Magh, 8 marks; 2072 Asoj, 5 marks; 2078 Baisakh, 5 marks (asked 3 times) - Video: [How Interrupts Work in Modern Computers](https://www.youtube.com/watch?v=G7bqvpAw7HE) — BitLemon - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_6/embedded_system/vectored-interrupt-io-flow - Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-5 ## Question Explain the operation of interrupt-driven I/O using vectored interrupt (write down each step for peripheral to memory transfer without DMA using vectored interrupt). ## Short answer In vectored interrupt I/O, the peripheral asserts an interrupt. The CPU acknowledges and the peripheral sends a vector number on the data bus. The CPU uses the vector to index into the interrupt vector table to find the ISR. The ISR reads data from the peripheral and writes to memory, then returns, avoiding polling. ## Answer In **interrupt-driven I/O with a vectored interrupt**, the peripheral supplies the processor with a number (the interrupt vector) that identifies which interrupt service routine (ISR) to run. The processor does not need to poll the devices, and the ISR location is not fixed. Example: a peripheral transfers a byte to memory without DMA. The data is in the peripheral register Reg, and the ISR copies it to memory address 500. #### Flow of actions ```text Processor Peripheral Memory | main program running | | |<---- Int (request) ----| | |----- Inta (ack) ------>| | |<--- Vector (data bus) -| | | look up IVT, ISR addr | | | save PC, jump to ISR | | | ISR: read Reg -> store |-------------->| M[500]=data | return, restore PC | | ``` #### Steps 1. The processor is executing its main program (e.g. the instruction at PC = 100). 2. The peripheral has data ready and asserts the interrupt request **Int** to the processor. 3. The processor finishes the current instruction and, if interrupts are enabled, saves the PC (and flags) on the stack. 4. The processor asserts **Inta** (interrupt acknowledge) on the control bus. 5. The peripheral puts its **interrupt vector number** (or the ISR address) on the data bus and removes Int. 6. The processor reads the vector, finds the ISR address in the **interrupt vector table (IVT)** (at vector x entry size), and loads it into the PC. 7. The ISR executes: it reads the data from the peripheral register (e.g. R0 = Reg) and writes it to memory (M[500] = R0). 8. The ISR ends with a return-from-interrupt instruction; the processor restores the PC (and flags) from the stack and resumes the main program. **Advantage:** several devices can each supply their own vector, so the processor reaches the right ISR without polling; this is more flexible than a fixed ISR location. **Disadvantage:** the device needs hardware to supply the vector, and the processor is still involved in every transfer. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What does the peripheral place on the data bus in vectored interrupt? A. Its interrupt vector number (or ISR address) B. The data to store C. The memory address 100 D. Nothing Answer: A. The vector identifies the ISR, so no polling is needed. (Key point: Role of the vector) 2. After the peripheral asserts Int, what does the processor do? A. Finishes the current instruction, saves PC, then asserts Inta B. Asserts Inta then saves PC C. Jumps to the ISR directly D. Starts polling Answer: A. The processor finishes the instruction, saves PC (and flags), then acknowledges with Inta. (Key point: Order of steps) 3. How does the processor find the ISR address? A. Looks up the interrupt vector table using the vector B. Reads it from the peripheral register C. Uses a fixed address D. Reads the stack Answer: A. The vector x entry size indexes the IVT, giving the ISR address loaded into the PC. (Key point: Finding the ISR) 4. What does the ISR do in this example? A. Reads the peripheral register and stores it in M[100], then returns restoring PC B. Writes M[100] into Reg C. Sets up DMA registers D. Disables the peripheral Answer: A. R0 = Reg; M[100] = R0; return-from-interrupt restores the PC. (Key point: ISR work and return) ## Related in Embedded System - [DMA controller and flow of actions](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Adma-controller-flow) — Embedded System, chapter 5, asked 3× - [Interrupt and fixed ISR flow of actions](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Ainterrupt-fixed-isr-flow) — Embedded System, chapter 5 - [Arbitration and memory-mapped vs standard I/O](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aarbitration-memory-mapped-io) — Embedded System, chapter 5 ## Related in other subjects - [Programmed vs interrupt-driven vs DMA](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aio-techniques-compare) — Computer Organization and Architecture, chapter 7, asked 5× - [DMA vs programmed and interrupt-driven I/O](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adma-overcomes) — Computer Organization and Architecture, chapter 7, asked 3× - [Interrupt driven data transfer](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Ainterrupt-driven-transfer) — Instrumentation II, chapter 1, asked 2× - [Compare status check I/O, interrupt I/O and DMA](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Acompare-status-interrupt-dma) — Instrumentation II, chapter 1