---
title: "VHDL architectures; elevator controller"
subject: "Embedded System"
chapter: 9
key: "semester_6/embedded_system:vhdl-architectures-elevator"
source: https://www.bctengineer.com/q/semester_6/embedded_system/vhdl-architectures-elevator
site: BCT Engineering
---

# VHDL architectures; elevator controller

Embedded System · Chapter 9: Microcontrollers in Embedded Systems

- Asked in: 2078 Baisakh, 2+6 marks
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/embedded_system/vhdl-architectures-elevator
- Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-9

## Question

Explain different architecture in VHDL. Write a VHDL code to design an elevator's control unit with necessary assumptions using state machine.

## Short answer

VHDL architectures model an entity in three styles: behavioral (sequential process), dataflow (concurrent signal assignments), and structural (component instances). The elevator FSM assumes 4 floors, stored requests, one clock per floor move, 4-clock door open; states are IDLE, MOVE_UP, MOVE_DOWN, DOOR with transitions based on pending requests above/below and door timer.

## Answer

#### Architectures (modelling styles) in VHDL

An entity describes the interface; its **architecture** describes the internal working. One entity can have several architectures, each in one of three styles:

1. **Behavioral:** describes what the circuit does using sequential statements inside a `process` (if, case, loops), without specifying gates.
```vhdl
architecture behav of mux2 is
begin
  process (a, b, s)
  begin
    if s = '0' then y <= a; else y <= b; end if;
  end process;
end architecture;
```
2. **Dataflow (RTL):** describes how data flows between signals using concurrent signal assignments, e.g. `y <= (a and not s) or (b and s);` or `with ... select`.
3. **Structural:** describes the circuit as interconnected components (instances with port maps), like a netlist of gates and sub-blocks.

#### Elevator control unit

**Assumptions:** 4 floors (0-3); `req(3:0)` are the floor buttons (inside and outside, one bit per floor), which are stored until served; the cabin needs one clock to move one floor; the door stays open for 4 clocks; when requests exist both above and below, the cabin serves upward requests first.

**Outputs:** floor (current floor), `up`, `down` (motor) and `door_open`.

**States:**

| State | Meaning | Next state |
|---|---|---|
| IDLE | Waiting; examines stored requests | DOOR if request for the current floor; MOVE_UP if a request above; MOVE_DOWN if a request below; else IDLE |
| MOVE_UP | Motor up, floor = floor + 1 | IDLE |
| MOVE_DOWN | Motor down, floor = floor - 1 | IDLE |
| DOOR | Door open, timer counts 3 down to 0, the request for this floor is cleared | IDLE when the timer reaches 0 |

```text
 IDLE --request for this floor--> DOOR
 IDLE --request above-----------> MOVE_UP
 IDLE --request below-----------> MOVE_DOWN
 MOVE_UP / MOVE_DOWN --(1 clock, floor +/- 1)--> IDLE
 DOOR --timer = 0--> IDLE
```

```vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- 4-floor elevator control unit (floors 0..3)
entity elevator is
  port (
    clk       : in  std_logic;
    rst       : in  std_logic;                      -- active high
    req       : in  std_logic_vector(3 downto 0);   -- floor buttons (inside + outside)
    floor     : out unsigned(1 downto 0);           -- current floor
    up        : out std_logic;                      -- motor up
    down      : out std_logic;                      -- motor down
    door_open : out std_logic                       -- door open
  );
end entity elevator;

architecture fsm of elevator is
  type state_t is (IDLE, MOVE_UP, MOVE_DOWN, DOOR);
  signal state   : state_t;
  signal cur     : unsigned(1 downto 0);            -- current floor register
  signal pending : std_logic_vector(3 downto 0);    -- stored requests
  signal timer   : unsigned(1 downto 0);            -- door-open time
begin
  process (clk, rst)
    variable pend  : std_logic_vector(3 downto 0);
    variable above : boolean;
    variable below : boolean;
  begin
    if rst = '1' then
      state   <= IDLE;
      cur     <= (others => '0');                   -- start at ground floor
      pending <= (others => '0');
      timer   <= (others => '0');
    elsif rising_edge(clk) then
      pend := pending or req;                       -- remember new requests
      above := false;
      below := false;
      for i in 0 to 3 loop
        if pend(i) = '1' then
          if i > to_integer(cur) then above := true; end if;
          if i < to_integer(cur) then below := true; end if;
        end if;
      end loop;

      case state is
        when IDLE =>
          if pend(to_integer(cur)) = '1' then       -- request for this floor
            pend(to_integer(cur)) := '0';           -- clear it
            timer <= "11";
            state <= DOOR;
          elsif above then
            state <= MOVE_UP;
          elsif below then
            state <= MOVE_DOWN;
          end if;
        when MOVE_UP =>
          cur   <= cur + 1;                         -- one floor per clock
          state <= IDLE;
        when MOVE_DOWN =>
          cur   <= cur - 1;
          state <= IDLE;
        when DOOR =>
          if timer = 0 then
            state <= IDLE;                          -- close door
          else
            timer <= timer - 1;
          end if;
      end case;
      pending <= pend;
    end if;
  end process;

  floor     <= cur;
  up        <= '1' when state = MOVE_UP   else '0';
  down      <= '1' when state = MOVE_DOWN else '0';
  door_open <= '1' when state = DOOR      else '0';
end architecture fsm;
```

The design was analysed and simulated with GHDL: a request for floor 3 from floor 0 moves the car up and opens the door at floor 3; a later request for floor 1 moves it down to floor 1; simultaneous requests for floors 0 and 2 serve floor 2 first and then 0.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Which are the three VHDL architecture styles?
   A. Behavioral, dataflow and structural
   B. Entity, package and library
   C. Static, dynamic and mixed
   D. Signal, variable and constant
   Answer: A. Architectures are written in behavioral, dataflow (RTL) or structural style. (Key point: Modelling styles)

2. What does a structural architecture describe?
   A. An algorithm inside a process
   B. Boolean equations only
   C. Interconnected components using port maps
   D. Test bench stimuli
   Answer: C. Structural modelling instantiates components and connects them like a netlist. (Key point: Structural style)

3. In the elevator FSM, which state follows MOVE_UP after one clock?
   A. DOOR
   B. MOVE_DOWN
   C. IDLE
   D. MOVE_UP
   Answer: C. Moving one floor takes one clock and the machine returns to IDLE to re-examine requests. (Key point: Elevator FSM states)

4. Why are requests kept in a pending register?
   A. So a button press is remembered until the floor is served
   B. To count floors
   C. To slow the clock
   D. To drive the motor
   Answer: A. pending = pending or req stores requests until they are cleared on arrival. (Key point: Request storage)

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