---
title: "VHDL COMPONENT; JK flip-flop with PROCESS"
subject: "Embedded System"
chapter: 9
key: "semester_6/embedded_system:vhdl-component-jk-ff"
source: https://www.bctengineer.com/q/semester_6/embedded_system/vhdl-component-jk-ff
site: BCT Engineering
---

# VHDL COMPONENT; JK flip-flop with PROCESS

Embedded System · Chapter 9: Microcontrollers in Embedded Systems

- Asked in: 2075 Baisakh, 3+5 marks
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/embedded_system/vhdl-component-jk-ff
- Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-9

## Question

Explain COMPONENT with its declaration. Write a VHDL code for a JK flip-flop using PROCESS.

## Short answer

A component is a reusable design unit declared with ports and instantiated using port map. A JK flip-flop process is sensitive to clk and rst; if rst='1' then q_int<='0'; elsif rising_edge(clk) then JK=00 hold, 01 reset, 10 set, 11 toggle.

## Answer

#### Component

A **component** is a design unit (an entity) that is used as a building block inside another design. It must first be declared and then instantiated.

**Component declaration** (in the architecture's declarative part or in a package) lists the name and ports of the entity to be used:

```vhdl
component component_name
  port ( port_name : mode type; ... );
end component;
```

**Component instantiation** (in the architecture body) places it and connects its ports:

```vhdl
label : component_name port map (formal1 => actual1, formal2 => actual2);
```

The declaration must match the entity's ports. Components allow hierarchy, reuse and structural description. For example, to use the JK flip-flop below as a component (say, twice in a larger design), declare:

```vhdl
component jkff
  port (clk, rst, j, k : in std_logic; q, qn : out std_logic);
end component;
```

#### JK flip-flop using a process

```vhdl
library ieee;
use ieee.std_logic_1164.all;

entity jkff is
  port (
    clk : in  std_logic;
    rst : in  std_logic;       -- asynchronous reset, active high
    j   : in  std_logic;
    k   : in  std_logic;
    q   : out std_logic;
    qn  : out std_logic
  );
end entity jkff;

architecture behavioral of jkff is
  signal q_int : std_logic := '0';      -- internal copy of the state
begin
  process (clk, rst)
  begin
    if rst = '1' then
      q_int <= '0';
    elsif rising_edge(clk) then
      if    j = '0' and k = '0' then q_int <= q_int;       -- hold
      elsif j = '0' and k = '1' then q_int <= '0';         -- reset
      elsif j = '1' and k = '0' then q_int <= '1';         -- set
      else                           q_int <= not q_int;   -- toggle
      end if;
    end if;
  end process;

  q  <= q_int;
  qn <= not q_int;
end architecture behavioral;
```

Operation on the rising edge of `clk`: JK = 00 holds Q; 01 resets Q to 0; 10 sets Q to 1; 11 toggles Q. The asynchronous `rst` clears Q at any time. The code was analysed and simulated with GHDL.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What is a component in VHDL?
   A. A design unit (entity) used as a building block inside another design, after being declared and instantiated
   B. A signal that carries data between two processes
   C. A library that holds the std_logic type
   D. A sequential statement used inside a process
   Answer: A. A component lets an existing entity be reused inside another design, giving hierarchy and structural description. It must be declared and then instantiated. (Key point: Purpose of a component)

2. Where is a component declared, and how is it then connected in the design?
   A. Declared in the entity; connected with a process
   B. Declared in the architecture declarative part (or a package); connected in the architecture body with a label and port map
   C. Declared in the architecture body; connected with a signal assignment
   D. Declared in a package only; connected with a generic
   Answer: B. The component declaration lists the name and ports, and goes in the architecture declarative part or a package. Instantiation uses label : component_name port map (...) in the architecture body. (Key point: Declaration vs instantiation)

3. On the rising clock edge, what does the JK flip-flop code do when J = 1 and K = 1?
   A. Holds Q
   B. Resets Q to 0
   C. Sets Q to 1
   D. Toggles Q
   Answer: D. J K = 11 executes q_int <= not q_int, so Q toggles. 00 holds, 01 resets, 10 sets. (Key point: JK flip-flop truth behaviour)

4. Why are both clk and rst in the process sensitivity list, with rst tested before rising_edge(clk)?
   A. So the reset only acts on a clock edge
   B. So Q is cleared at any time rst = '1', independent of the clock
   C. So the flip-flop toggles whenever rst changes
   D. So the process runs only once at start-up
   Answer: B. Testing rst first outside the clock-edge condition and having it in the sensitivity list makes it asynchronous: it clears Q at any time. (Key point: Asynchronous reset in process)

## Related in Embedded System

- [VHDL dataflow/behavioural models; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-dataflow-behavioural-jk) — Embedded System, chapter 9
- [VHDL entity, architecture; D flip-flop](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-entity-architecture-dff) — Embedded System, chapter 9
- [VHDL entity declaration; T flip-flops circuit](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-entity-two-tff-inverter) — Embedded System, chapter 9
- [VHDL PROCESS; full adder with half adders](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-process-full-adder) — Embedded System, chapter 9

## Related in other subjects

- [SR drawback; edge triggered JK flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-drawback-edge-jk) — Digital Logic, chapter 6, asked 3×
- [SR to JK flip-flop conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-to-jk-conversion) — Digital Logic, chapter 6, asked 2×
- [JK flip-flop characteristic and excitation tables](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-flipflop-characteristic-excitation) — Digital Logic, chapter 6, asked 2×
- [T to JK flip-flop conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3At-to-jk-conversion) — Digital Logic, chapter 6, asked 2×