--- title: "VHDL dataflow/behavioural models; JK flip-flop" subject: "Embedded System" chapter: 9 key: "semester_6/embedded_system:vhdl-dataflow-behavioural-jk" source: https://www.bctengineer.com/q/semester_6/embedded_system/vhdl-dataflow-behavioural-jk site: BCT Engineering --- # VHDL dataflow/behavioural models; JK flip-flop Embedded System · Chapter 9: Microcontrollers in Embedded Systems - Asked in: 2078 Poush - Video: [Behavioval Style of Modeling in VHDL | Digital Electronics | Digital Circuit Design in EXTC](https://www.youtube.com/watch?v=LV0bJZ2MTU8) — Ekeeda - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_6/embedded_system/vhdl-dataflow-behavioural-jk - Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-9 ## Question Explain dataflow and behavioural models in VHDL. Write a VHDL code for a JK flip-flop using PROCESS. ## Short answer Dataflow uses concurrent signal assignments (Boolean equations); behavioural uses a process with sequential statements. A JK flip-flop process with asynchronous reset: on rising edge, JK=00 holds, 01 resets, 10 sets, 11 toggles, using internal q_int. ## Answer #### Dataflow model The **dataflow model** describes a circuit by concurrent signal assignments that show how data flows from inputs to outputs, using Boolean equations or `when ... else` / `with ... select`. The order of statements does not matter; each statement is evaluated whenever a signal on its right-hand side changes. ```vhdl -- dataflow description of a half adder sum <= a xor b; carry <= a and b; ``` #### Behavioural model The **behavioural model** describes what the circuit does in an algorithmic way, using a `process` with sequential statements (if, case, loop). It does not say which gates are used. It is the best model for sequential circuits such as flip-flops, counters and state machines. | Point | Dataflow | Behavioural | |---|---|---| | Statements | Concurrent assignments | Sequential statements inside a process | | Describes | Flow of data / Boolean equations | Algorithm / functionality | | Typical use | Combinational logic | Sequential logic and FSMs | #### JK flip-flop using a process Characteristic table: JK = 00 hold, 01 reset, 10 set, 11 toggle. ```vhdl library ieee; use ieee.std_logic_1164.all; entity jkff is port ( clk : in std_logic; rst : in std_logic; -- asynchronous reset, active high j : in std_logic; k : in std_logic; q : out std_logic; qn : out std_logic ); end entity jkff; architecture behavioral of jkff is signal q_int : std_logic := '0'; -- internal copy of the state begin process (clk, rst) begin if rst = '1' then q_int <= '0'; elsif rising_edge(clk) then if j = '0' and k = '0' then q_int <= q_int; -- hold elsif j = '0' and k = '1' then q_int <= '0'; -- reset elsif j = '1' and k = '0' then q_int <= '1'; -- set else q_int <= not q_int; -- toggle end if; end if; end process; q <= q_int; qn <= not q_int; end architecture behavioral; ``` The process is sensitive to `clk` and `rst`. The internal signal `q_int` is used so that `q` can be read back for the toggle and for `qn`. The code was analysed and simulated with GHDL for set, hold, toggle and reset. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What characterises the dataflow model? A. Sequential statements in a process B. Concurrent signal assignments, where statement order does not matter C. Component instances only D. Wait statements Answer: B. Dataflow uses concurrent assignments evaluated whenever right-hand-side signals change. (Key point: Dataflow model) 2. What is the behavioural model best suited to? A. Sequential logic such as flip-flops, counters and FSMs B. Pure gates C. Netlists D. Pin assignment Answer: A. Processes with sequential statements describe algorithms and sequential circuits. (Key point: Behavioural model) 3. What does a JK flip-flop do when J = 1, K = 1? A. Holds B. Resets C. Toggles D. Sets Answer: C. JK = 00 hold, 01 reset, 10 set, 11 toggle. (Key point: JK table) 4. Why is the internal signal q_int used in the JK code? A. So q can be read back for toggling and for qn B. To speed up simulation C. Because ports cannot be assigned D. To avoid the clock Answer: A. An out port cannot be read, so the state is kept in q_int and copied to q and qn. (Key point: Internal signal) ## Related in Embedded System - [VHDL COMPONENT; JK flip-flop with PROCESS](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-component-jk-ff) — Embedded System, chapter 9 - [VHDL entity, architecture; D flip-flop](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-entity-architecture-dff) — Embedded System, chapter 9 - [VHDL entity declaration; T flip-flops circuit](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-entity-two-tff-inverter) — Embedded System, chapter 9 - [VHDL models; full adder structural](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-models-full-adder-structural) — Embedded System, chapter 9 - [VHDL PROCESS; full adder with half adders](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-process-full-adder) — Embedded System, chapter 9 ## Related in other subjects - [SR drawback; edge triggered JK flip-flop](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-drawback-edge-jk) — Digital Logic, chapter 6, asked 3× - [SR to JK flip-flop conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-to-jk-conversion) — Digital Logic, chapter 6, asked 2× - [JK flip-flop characteristic and excitation tables](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Ajk-flipflop-characteristic-excitation) — Digital Logic, chapter 6, asked 2× - [T to JK flip-flop conversion](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3At-to-jk-conversion) — Digital Logic, chapter 6, asked 2×