---
title: "VHDL entity, architecture; D flip-flop"
subject: "Embedded System"
chapter: 9
key: "semester_6/embedded_system:vhdl-entity-architecture-dff"
source: https://www.bctengineer.com/q/semester_6/embedded_system/vhdl-entity-architecture-dff
site: BCT Engineering
---

# VHDL entity, architecture; D flip-flop

Embedded System · Chapter 9: Microcontrollers in Embedded Systems

- Asked in: 2079 Jestha
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/embedded_system/vhdl-entity-architecture-dff
- Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-9

## Question

Explain entity and architecture of VHDL declaration. Write VHDL code for a D flip-flop using process.

## Short answer

An entity declares the design's interface (name, ports with mode and type); an architecture defines its internal behavior using behavioral, dataflow, or structural code. A D flip-flop with asynchronous active-high reset uses a process sensitive to clk and rst: if rst='1' then q<='0'; elsif rising_edge(clk) then q<=d; end if.

## Answer

#### Entity

The **entity declaration** defines the external interface of a design unit: its name, and its ports (name, direction in/out/inout/buffer, and type). It is like the symbol or black box of the circuit.

```vhdl
entity name is
  port ( signal_name : mode type; ... );
end entity name;
```

#### Architecture

The **architecture body** defines what the entity does, using behavioral, dataflow or structural description. It has a declarative part (signals, components, types) and a statement part between `begin` and `end`. One entity can have several architectures.

```vhdl
architecture arch_name of entity_name is
  -- declarations (signals, components, constants)
begin
  -- concurrent statements, processes, component instances
end architecture arch_name;
```

#### D flip-flop using a process

The flip-flop copies D to Q at the rising edge of the clock; an asynchronous active-high reset clears Q.

```vhdl
library ieee;
use ieee.std_logic_1164.all;

entity dff is
  port (
    clk : in  std_logic;
    rst : in  std_logic;       -- asynchronous reset, active high
    d   : in  std_logic;
    q   : out std_logic
  );
end entity dff;

architecture behavioral of dff is
begin
  process (clk, rst)
  begin
    if rst = '1' then
      q <= '0';                         -- reset overrides the clock
    elsif rising_edge(clk) then
      q <= d;                           -- store D on the rising edge
    end if;
  end process;
end architecture behavioral;
```

The process is sensitive to `clk` and `rst`. When `rst = '1'` the output is cleared at once; otherwise on `rising_edge(clk)` the value of `d` is stored. Between edges q keeps its value, which makes the process infer a flip-flop. The code was checked with GHDL.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What does the entity declaration define?
   A. The internal logic
   B. The external interface: name and ports with direction and type
   C. The simulation time
   D. The clock frequency
   Answer: B. The entity is the black-box interface with its ports. (Key point: Entity)

2. What does the architecture body define?
   A. Only the port names
   B. How the entity works, using behavioral, dataflow or structural description
   C. The FPGA pinout
   D. The library list
   Answer: B. The architecture holds the internal description; one entity can have several. (Key point: Architecture)

3. When does the D flip-flop process store D into Q?
   A. Whenever d changes
   B. At the rising edge of clk, if rst is not active
   C. Only when rst = 1
   D. At the falling edge
   Answer: B. rising_edge(clk) copies d to q; between edges q keeps its value. (Key point: Clocked storage)

4. What does the asynchronous reset do?
   A. Waits for the clock edge
   B. Clears Q immediately when rst = 1, overriding the clock
   C. Sets Q to 1
   D. Has no effect
   Answer: B. The reset branch is tested first and clears q at once. (Key point: Asynchronous reset)

## Related in Embedded System

- [VHDL entity declaration; T flip-flops circuit](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-entity-two-tff-inverter) — Embedded System, chapter 9
- [VHDL COMPONENT; JK flip-flop with PROCESS](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-component-jk-ff) — Embedded System, chapter 9
- [VHDL dataflow/behavioural models; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-dataflow-behavioural-jk) — Embedded System, chapter 9
- [VHDL PROCESS; full adder with half adders](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-process-full-adder) — Embedded System, chapter 9