---
title: "VHDL entity declaration; T flip-flops circuit"
subject: "Embedded System"
chapter: 9
key: "semester_6/embedded_system:vhdl-entity-two-tff-inverter"
source: https://www.bctengineer.com/q/semester_6/embedded_system/vhdl-entity-two-tff-inverter
site: BCT Engineering
---

# VHDL entity declaration; T flip-flops circuit

Embedded System · Chapter 9: Microcontrollers in Embedded Systems

- Asked in: 2071 Magh, 3+5 marks
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/embedded_system/vhdl-entity-two-tff-inverter
- Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-9

## Question

How is an entity declared in VHDL programming? A circuit composed of two T-flip flops and an inverter shown in figure below, convert it into VHDL code. [Figure: circuit COUNT2 with two T flip-flops and an inverter. CLOCK drives the CK input of T flip-flop BIT_0; BIT_0 output Q is FF0 (also output Q0) and feeds input A of INVERTER INV; the inverter output Y (INV_FF0) drives the CK input of T flip-flop BIT_1; BIT_1 output Q is FF1 (output Q1)]

## Short answer

An entity declares the interface with a name and a port list specifying signal names, modes (in, out) and types, terminated by 'end entity'. The circuit uses two tff_ck components and an inverter; BIT_0 toggles on CLOCK rising edge, its inverted output clocks BIT_1, forming a 2-bit asynchronous counter.

## Answer

#### Entity declaration

An entity is declared with the keyword `entity`, a name, and a `port` list giving each port's name, mode (`in`, `out`, `inout`, `buffer`) and type, closed by `end entity`:

```vhdl
entity count2 is
  port (
    clock : in  std_logic;
    q0    : out std_logic;
    q1    : out std_logic
  );
end entity count2;
```

The architecture then defines the contents.

#### COUNT2 circuit

The figure shows a 2-bit asynchronous counter: BIT_0 is clocked by CLOCK, the inverter output INV_FF0 clocks BIT_1. The T input of each flip-flop is taken as permanently 1, so each toggles on every rising clock edge. It is a structural description with components `tff_ck` (toggle flip-flop with only the clock input CK and output Q) and `inverter`.

```vhdl
library ieee;
use ieee.std_logic_1164.all;

-- Basic components (the T input is taken as permanently '1': toggle on every clock edge)
entity tff_ck is
  port (ck : in std_logic; q : out std_logic);
end entity tff_ck;

architecture behavioral of tff_ck is
  signal state : std_logic := '0';
begin
  process (ck)
  begin
    if rising_edge(ck) then
      state <= not state;
    end if;
  end process;
  q <= state;
end architecture behavioral;

library ieee;
use ieee.std_logic_1164.all;

entity inverter is
  port (a : in std_logic; y : out std_logic);
end entity inverter;

architecture dataflow of inverter is
begin
  y <= not a;
end architecture dataflow;

library ieee;
use ieee.std_logic_1164.all;

entity count2 is
  port (
    clock : in  std_logic;
    q0    : out std_logic;
    q1    : out std_logic
  );
end entity count2;

architecture structural of count2 is
  component tff_ck
    port (ck : in std_logic; q : out std_logic);
  end component;
  component inverter
    port (a : in std_logic; y : out std_logic);
  end component;

  signal ff0     : std_logic;        -- output of BIT_0
  signal inv_ff0 : std_logic;        -- output of INV
  signal ff1     : std_logic;        -- output of BIT_1
begin
  bit_0 : tff_ck  port map (ck => clock,   q => ff0);
  inv   : inverter port map (a  => ff0,     y => inv_ff0);
  bit_1 : tff_ck  port map (ck => inv_ff0, q => ff1);

  q0 <= ff0;
  q1 <= ff1;
end architecture structural;
```

Signals `ff0`, `inv_ff0` and `ff1` are the internal wires of the figure. Q0 toggles on each rising edge of CLOCK. BIT_1 is clocked by the inverted Q0, i.e. on each falling edge of Q0, so the pair counts 00, 01, 10, 11, 00 ... on successive clock edges (checked with a GHDL simulation; the flip-flops have an initial value 0).

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How is an entity declared in VHDL?
   A. With the keyword entity, a name, and a port list giving each port's name, mode and type, closed by end entity
   B. With the keyword architecture and a signal list
   C. With the keyword component followed by a process
   D. With a package and a use clause only
   Answer: A. An entity has a name and a port list (name : mode type), ending with end entity; the architecture defines the contents. (Key point: Entity declaration)

2. Which set lists the port modes available in an entity?
   A. in, out, signal, variable
   B. in, out, inout, buffer
   C. read, write, both, none
   D. input, output, wire, reg
   Answer: B. The port modes are in, out, inout and buffer. (Key point: Port modes)

3. In COUNT2, what clocks the second flip-flop BIT_1?
   A. CLOCK directly
   B. Output Q of BIT_1 itself
   C. The inverter output INV_FF0, i.e. the inverted Q0 of BIT_0
   D. A separate reset signal
   Answer: C. BIT_0 output FF0 goes through the inverter and the result INV_FF0 drives the CK of BIT_1, making it an asynchronous (ripple) counter. (Key point: Clocking of BIT_1)

4. Why does the circuit count 00, 01, 10, 11, 00 ...?
   A. BIT_0 toggles every clock rising edge, and BIT_1 toggles on each falling edge of Q0
   B. Both flip-flops toggle only on the falling edge of CLOCK
   C. BIT_1 toggles on every clock edge and BIT_0 on every second one
   D. The inverter makes BIT_0 toggle twice per clock
   Answer: A. Q0 toggles each rising clock edge. The inverted Q0 rises when Q0 falls, so Q1 toggles once every two clocks, giving a binary count. (Key point: Counting sequence)

## Related in Embedded System

- [VHDL entity, architecture; D flip-flop](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-entity-architecture-dff) — Embedded System, chapter 9
- [VHDL COMPONENT; JK flip-flop with PROCESS](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-component-jk-ff) — Embedded System, chapter 9
- [VHDL dataflow/behavioural models; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-dataflow-behavioural-jk) — Embedded System, chapter 9

## Related in other subjects

- [Types of flip-flops; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Aflip-flop-types-jk) — Basic Electronics Engineering, chapter 6, asked 2×
- [Sequence detector 101 using T flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Adetector-101-t) — Digital Logic, chapter 9
- [Edge triggered JK flip-flop circuit](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aedge-jk-circuit) — Digital Logic, chapter 6
- [SR equation; mod-5 counter using D flip-flops](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Asr-equation-mod5-d-counter) — Digital Logic, chapter 8