---
title: "VHDL models; full adder structural"
subject: "Embedded System"
chapter: 9
key: "semester_6/embedded_system:vhdl-models-full-adder-structural"
source: https://www.bctengineer.com/q/semester_6/embedded_system/vhdl-models-full-adder-structural
site: BCT Engineering
---

# VHDL models; full adder structural

Embedded System · Chapter 9: Microcontrollers in Embedded Systems

- Asked in: 2075 Bhadra, 3+5 marks
- Video: [Modeling Style in VHDL || VLSI Unit1 ch. 3](https://www.youtube.com/watch?v=-7ZbujXMNBI) — Education Arena
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/embedded_system/vhdl-models-full-adder-structural
- Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-9

## Question

Explain different models in VHDL. Write a VHDL code for a full adder using two half adders and one OR gate in structural model.

## Short answer

Behavioral describes algorithmically, dataflow uses concurrent Boolean, structural interconnects components. A full adder from two half adders and OR gate: HA1→s1, c1; HA2 with cin→sum, c2; cout = c1 OR c2, instantiated with port maps.

## Answer

#### Models in VHDL

1. **Behavioral model:** describes the function algorithmically inside processes (if/case), without describing the gate structure. Example: `process (a,b,cin) ... sum <= ...`.
2. **Dataflow model:** concurrent signal assignments with Boolean expressions, showing the flow of data: `sum <= a xor b xor cin;`.
3. **Structural model:** interconnection of components using port maps, like a netlist; it reflects the real hardware hierarchy.
4. **Mixed model:** a combination of the above in one architecture.

#### Full adder from two half adders and an OR gate

```text
        +-------+  s1   +-------+
 a ---->|       |------>|       |----> sum
 b ---->|  HA1  |  cin->|  HA2  |
        +-------+       +-------+
           | c1             | c2
           |   +------+     |
           +-->|  OR  |<----+
               +------+
                  |
                  v
                 cout
```

HA1 adds a and b, giving s1 and c1; HA2 adds s1 and cin, giving sum and c2; cout = c1 OR c2.

```vhdl
library ieee;
use ieee.std_logic_1164.all;

entity half_adder is
  port (a, b : in std_logic; sum, carry : out std_logic);
end entity half_adder;

architecture dataflow of half_adder is
begin
  sum   <= a xor b;
  carry <= a and b;
end architecture dataflow;

library ieee;
use ieee.std_logic_1164.all;

entity or2 is
  port (a, b : in std_logic; y : out std_logic);
end entity or2;

architecture dataflow of or2 is
begin
  y <= a or b;
end architecture dataflow;

library ieee;
use ieee.std_logic_1164.all;

entity full_adder is
  port (
    a, b, cin : in  std_logic;
    sum, cout : out std_logic
  );
end entity full_adder;

architecture structural of full_adder is
  component half_adder
    port (a, b : in std_logic; sum, carry : out std_logic);
  end component;
  component or2
    port (a, b : in std_logic; y : out std_logic);
  end component;

  signal s1, c1, c2 : std_logic;     -- internal wires
begin
  ha1 : half_adder port map (a => a,  b => b,   sum => s1,  carry => c1);
  ha2 : half_adder port map (a => s1, b => cin, sum => sum, carry => c2);
  o1  : or2        port map (a => c1, b => c2,  y => cout);
end architecture structural;
```

The structural description was analysed and simulated with GHDL for all 8 input combinations (sum = a xor b xor cin, cout = majority of a, b, cin).

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Which VHDL model uses concurrent signal assignments with Boolean expressions, such as sum <= a xor b xor cin;?
   A. Behavioral
   B. Structural
   C. Dataflow
   D. Mixed
   Answer: C. The dataflow model shows how data flows using concurrent signal assignments of Boolean expressions. (Key point: Dataflow model)

2. What characterises the structural model?
   A. Algorithmic description inside processes using if/case
   B. Interconnection of components with port maps, like a netlist
   C. A single Boolean expression per output
   D. A combination of the other models in one architecture
   Answer: B. A structural description is a netlist of components joined by port maps, reflecting the real hardware hierarchy. (Key point: Structural model)

3. In the full adder built from two half adders and an OR gate, what are the inputs of the second half adder (HA2)?
   A. a and b
   B. c1 and c2
   C. s1 (sum of HA1) and cin
   D. a and cin
   Answer: C. HA1 adds a and b to give s1 and c1. HA2 adds s1 and cin to give the final sum and carry c2. (Key point: Full adder wiring)

4. How is the carry out cout obtained in this structure?
   A. cout = c1 and c2
   B. cout = c1 xor c2
   C. cout = c1 or c2
   D. cout = s1 or cin
   Answer: C. A carry is produced by either half adder (never both), so cout = c1 OR c2, implemented by the OR gate. (Key point: Carry out)

## Related in Embedded System

- [VHDL PROCESS; full adder with half adders](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-process-full-adder) — Embedded System, chapter 9
- [VHDL dataflow/behavioural models; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-dataflow-behavioural-jk) — Embedded System, chapter 9

## Related in other subjects

- [Full adder from half adders](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-half-adders) — Digital Logic, chapter 5
- [2-bit fast adder; full subtractor from half subtractors](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afast-adder-full-subtractor) — Digital Logic, chapter 5
- [Σ(0,2,3,5,8,12,14) using 8:1 MUX; add with full adders](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-8to1-add-full-adders) — Digital Logic, chapter 4