--- title: "VHDL PROCESS; full adder with half adders" subject: "Embedded System" chapter: 9 key: "semester_6/embedded_system:vhdl-process-full-adder" source: https://www.bctengineer.com/q/semester_6/embedded_system/vhdl-process-full-adder site: BCT Engineering --- # VHDL PROCESS; full adder with half adders Embedded System · Chapter 9: Microcontrollers in Embedded Systems - Asked in: 2073 Magh, 3+5 marks - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_6/embedded_system/vhdl-process-full-adder - Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-9 ## Question Explain PROCESS in VHDL. Write a VHDL code for a full adder using 2 half adders as component. ## Short answer A process contains sequential statements, executes when sensitivity signals change, with signal updates after delta delay. A full adder uses two half-adder components: each half adder's process yields sum (xor) and carry (and); connections via port map, cout = c1 OR c2. ## Answer #### PROCESS in VHDL A **process** is a concurrent statement that contains sequential statements (if, case, loops, signal and variable assignments). It is the basic way of writing behavioural descriptions. ```vhdl label : process (sensitivity_list) -- declarations (variables) begin -- sequential statements end process; ``` - It executes once at start-up, then whenever a signal in the **sensitivity list** changes, and suspends at `end process`. - Statements inside run in order; signal assignments take effect at the end of the process (after a delta delay). - Several processes in one architecture run concurrently. - A process with a clock edge (`rising_edge(clk)`) infers flip-flops; one sensitive to all inputs describes combinational logic. #### Full adder using two half adders as components The half adder is written with a process, and the full adder instantiates it twice: sum = (a xor b) xor cin, cout = c1 or c2. ```vhdl library ieee; use ieee.std_logic_1164.all; -- half adder described with a PROCESS entity half_adder is port ( a, b : in std_logic; s, c : out std_logic -- sum and carry ); end entity half_adder; architecture behavioral of half_adder is begin process (a, b) -- runs whenever a or b changes begin s <= a xor b; c <= a and b; end process; end architecture behavioral; library ieee; use ieee.std_logic_1164.all; -- full adder built from two half adders (components) and an OR entity full_adder is port ( x, y, cin : in std_logic; sum, cout : out std_logic ); end entity full_adder; architecture structural of full_adder is component half_adder port (a, b : in std_logic; s, c : out std_logic); end component; signal s1, c1, c2 : std_logic; begin u1 : half_adder port map (a => x, b => y, s => s1, c => c1); u2 : half_adder port map (a => s1, b => cin, s => sum, c => c2); cout <= c1 or c2; -- OR gate as a concurrent statement end architecture structural; ``` The component `half_adder` is declared in the architecture of `full_adder` and instantiated as `u1` and `u2` with `port map`. The code was analysed and simulated with GHDL for all 8 input combinations. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What kind of statement is a process? A. A concurrent statement that contains sequential statements B. A sequential statement that contains concurrent statements C. A declaration of a component D. A statement that runs only once at start-up Answer: A. A process is itself concurrent with other processes, but the statements inside run in order. (Key point: Nature of a process) 2. When does a process execute? A. Only when the simulation ends B. Once at start-up, then whenever a signal in its sensitivity list changes C. Only on every clock rising edge D. Continuously without ever suspending Answer: B. A process runs once at start-up, then is re-triggered by events on signals in the sensitivity list, and suspends at end process. (Key point: Sensitivity list) 3. When do signal assignments inside a process take effect? A. Immediately, at the line where they appear B. Before the process starts C. At the end of the process (after a delta delay) D. Only when the clock rises Answer: C. Signal updates are scheduled and applied after the process suspends, after a delta delay. (Key point: Signal assignment timing) 4. How does the full adder use the process-based half adder twice? A. It copies the process into the architecture twice B. It declares the half_adder component and instantiates it as u1 and u2 with port map C. It calls the half adder as a function D. It lists half_adder in the sensitivity list Answer: B. The component is declared once in the architecture and instantiated twice with different labels and port maps; the OR is done with cout <= c1 or c2. (Key point: Hierarchy with components) ## Related in Embedded System - [VHDL models; full adder structural](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-models-full-adder-structural) — Embedded System, chapter 9 - [VHDL COMPONENT; JK flip-flop with PROCESS](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-component-jk-ff) — Embedded System, chapter 9 - [VHDL entity, architecture; D flip-flop](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-entity-architecture-dff) — Embedded System, chapter 9 - [VHDL dataflow/behavioural models; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-dataflow-behavioural-jk) — Embedded System, chapter 9 ## Related in other subjects - [Full adder from half adders](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-half-adders) — Digital Logic, chapter 5 - [2-bit fast adder; full subtractor from half subtractors](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afast-adder-full-subtractor) — Digital Logic, chapter 5 - [Σ(0,2,3,5,8,12,14) using 8:1 MUX; add with full adders](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Amux-8to1-add-full-adders) — Digital Logic, chapter 4 - [Full adder using a single 1:4 DEMUX](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Afull-adder-1to4-demux) — Digital Logic, chapter 4, asked 5×