---
title: "Structural modelling; 3-bit up counter"
subject: "Embedded System"
chapter: 9
key: "semester_6/embedded_system:vhdl-structural-3bit-counter"
source: https://www.bctengineer.com/q/semester_6/embedded_system/vhdl-structural-3bit-counter
site: BCT Engineering
---

# Structural modelling; 3-bit up counter

Embedded System · Chapter 9: Microcontrollers in Embedded Systems

- Asked in: 2079 Asoj, 8 marks
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/embedded_system/vhdl-structural-3bit-counter
- Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-9

## Question

What is structural modelling in VHDL? Design a 3-bit up counter using T flipflop using structural modeling in VHDL.

## Short answer

Structural modelling describes a design as interconnected components declared and instantiated via port maps. A 3-bit synchronous up counter uses T flip-flops: T0=1, T1=Q0, T2=Q0 AND Q1, all clocked together, counting from 000 to 111.

## Answer

#### Structural modelling

In **structural modelling** a design is described as a set of components connected by signals, like a schematic in text form. Each component is first declared (`component ... end component`) and then instantiated with a `port map` that connects its ports to signals or to the ports of the parent entity. It mirrors the hardware hierarchy, and is used to build large systems from smaller, tested blocks.

#### 3-bit up counter with T flip-flops

For a synchronous binary up counter, bit n toggles when all lower bits are 1:

- T0 = 1
- T1 = Q0
- T2 = Q0 . Q1

```text
           Q0            Q1            Q2
 '1' -> T FF0 --+--> T FF1 --+     T FF2
                |            |      ^
                +--[ AND ]---+------+   (t2 = Q0 and Q1)
 clk drives the clock input of all three flip-flops
```

Components: `tff` (T flip-flop, rising-edge clock, asynchronous reset) and `and2`.

| Clock | Q2 Q1 Q0 |
|---|---|
| reset | 0 0 0 |
| 1 | 0 0 1 |
| 2 | 0 1 0 |
| 3 | 0 1 1 |
| 4 | 1 0 0 |
| ... | counts to 1 1 1 and wraps to 0 0 0 |

```vhdl
library ieee;
use ieee.std_logic_1164.all;

-- T flip-flop: toggles on the rising clock edge when t = '1'
entity tff is
  port (clk, rst, t : in std_logic; q : out std_logic);
end entity tff;

architecture behavioral of tff is
  signal q_int : std_logic := '0';
begin
  process (clk, rst)
  begin
    if rst = '1' then
      q_int <= '0';
    elsif rising_edge(clk) then
      if t = '1' then
        q_int <= not q_int;
      end if;
    end if;
  end process;
  q <= q_int;
end architecture behavioral;

library ieee;
use ieee.std_logic_1164.all;

-- 2-input AND gate
entity and2 is
  port (a, b : in std_logic; y : out std_logic);
end entity and2;

architecture dataflow of and2 is
begin
  y <= a and b;
end architecture dataflow;

library ieee;
use ieee.std_logic_1164.all;

-- 3-bit synchronous up counter, structural description
entity counter3 is
  port (
    clk : in  std_logic;
    rst : in  std_logic;
    q   : out std_logic_vector(2 downto 0)
  );
end entity counter3;

architecture structural of counter3 is
  component tff
    port (clk, rst, t : in std_logic; q : out std_logic);
  end component;
  component and2
    port (a, b : in std_logic; y : out std_logic);
  end component;

  signal q0, q1, q2 : std_logic;     -- flip-flop outputs
  signal t2         : std_logic;     -- T input of the third flip-flop
begin
  -- T0 = 1, T1 = Q0, T2 = Q0 . Q1
  ff0 : tff  port map (clk => clk, rst => rst, t => '1', q => q0);
  ff1 : tff  port map (clk => clk, rst => rst, t => q0,  q => q1);
  g1  : and2 port map (a => q0, b => q1, y => t2);
  ff2 : tff  port map (clk => clk, rst => rst, t => t2,  q => q2);

  q <= q2 & q1 & q0;
end architecture structural;
```

The design was analysed and simulated with GHDL: the output counts 0,1,2,...,7,0,1,2 on successive clock edges.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How is a structural VHDL model built?
   A. With one process only
   B. By declaring components and instantiating them with port maps
   C. With concurrent Boolean equations only
   D. With wait statements
   Answer: B. Components are declared and instantiated with port maps, like a schematic in text. (Key point: Structural modelling)

2. For a synchronous 3-bit up counter, what are the T inputs?
   A. T0 = Q0, T1 = Q1, T2 = Q2
   B. T0 = 1, T1 = Q0, T2 = Q0 AND Q1
   C. T0 = 0, T1 = 1, T2 = 1
   D. T2 = Q0 OR Q1
   Answer: B. A bit toggles when all lower bits are 1. (Key point: T inputs)

3. What is the and2 component used for?
   A. Generating T2 = Q0 . Q1
   B. Resetting the counter
   C. Clock division
   D. Producing Q0
   Answer: A. The third flip-flop toggles only when both Q0 and Q1 are 1. (Key point: Role of AND gate)

4. How are the clock inputs connected?
   A. Each flip-flop clocks the next one
   B. The same clk drives all three flip-flops
   C. Only FF0 gets clk
   D. The AND gate drives clk
   Answer: B. All are clocked together, making it synchronous. (Key point: Clock connection)

## Related in Embedded System

- [VHDL models; full adder structural](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-models-full-adder-structural) — Embedded System, chapter 9
- [BCD counter 0-9999 on seven segment VHDL](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-bcd-counter-seven-segment) — Embedded System, chapter 9
- [Use of VHDL; decoder design](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-use-decoder) — Embedded System, chapter 9
- [Behavioral modeling; 2-input multiplexer](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-behavioral-mux) — Embedded System, chapter 9
- [VHDL entity declaration; T flip-flops circuit](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-entity-two-tff-inverter) — Embedded System, chapter 9
- [VHDL architectures; elevator controller](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-architectures-elevator) — Embedded System, chapter 9

## Related in other subjects

- [Sync vs async; 3-bit synchronous up counter (T)](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Async-up-counter-3bit-t) — Digital Logic, chapter 8
- [3-bit asynchronous up/down counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aasync-up-down-counter-3bit) — Digital Logic, chapter 8, asked 2×
- [3-bit Gray code synchronous counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Agray-code-sync-counter-3bit) — Digital Logic, chapter 8, asked 2×
- [Sync vs async; 3-bit synchronous down counter](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Async-down-counter-3bit) — Digital Logic, chapter 8