---
title: "Use of VHDL; decoder design"
subject: "Embedded System"
chapter: 9
key: "semester_6/embedded_system:vhdl-use-decoder"
source: https://www.bctengineer.com/q/semester_6/embedded_system/vhdl-use-decoder
site: BCT Engineering
---

# Use of VHDL; decoder design

Embedded System · Chapter 9: Microcontrollers in Embedded Systems

- Asked in: 2076 Baisakh, 2+6 marks
- Video: [VHDL code for Decoder and Realization on FPGA development Board](https://www.youtube.com/watch?v=IR3cQepKHV8) — Ekeeda
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/embedded_system/vhdl-use-decoder
- Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-9

## Question

What is the use of VHDL code in embedded system? Design and write a code for Decoder using VHDL.

## Short answer

VHDL describes digital hardware for simulation, synthesis to FPGA/ASIC, and hardware/software co-design; it creates custom peripherals and parallel processors. A 3-to-8 decoder with enable has inputs en and a(2:0), output y(7:0); behavioral VHDL uses a process with case statement to set one-hot y when en='1', else all zeros.

## Answer

#### Use of VHDL in embedded systems

VHDL (VHSIC Hardware Description Language) describes the structure and behaviour of digital hardware as text. In embedded systems it is used to:

- design **custom single-purpose processors** and peripherals (UART, timer, PWM, display controller) to run in parallel with the CPU;
- program **FPGAs/CPLDs**, or generate the layout of ASICs after synthesis;
- **simulate** and test the design before building hardware (test benches);
- reuse, document and port designs between devices and vendors;
- build hardware/software co-designs (soft-core processors with custom accelerators).

#### 3-to-8 decoder

A decoder with enable has 3 input lines a(2:0) and 8 outputs y(7:0); when en = 1 exactly one output, selected by the binary value of a, is high.

| en | a2 a1 a0 | y7 ... y0 |
|---|---|---|
| 0 | x x x | 00000000 |
| 1 | 0 0 0 | 00000001 |
| 1 | 0 0 1 | 00000010 |
| 1 | 0 1 0 | 00000100 |
| 1 | 0 1 1 | 00001000 |
| 1 | 1 0 0 | 00010000 |
| 1 | 1 0 1 | 00100000 |
| 1 | 1 1 0 | 01000000 |
| 1 | 1 1 1 | 10000000 |

```vhdl
library ieee;
use ieee.std_logic_1164.all;

entity decoder3to8 is
  port (
    en  : in  std_logic;                      -- enable
    a   : in  std_logic_vector(2 downto 0);   -- binary input
    y   : out std_logic_vector(7 downto 0)    -- one-hot output
  );
end entity decoder3to8;

architecture behavioral of decoder3to8 is
begin
  process (en, a)
  begin
    y <= (others => '0');                     -- default: all outputs low
    if en = '1' then
      case a is
        when "000"  => y <= "00000001";
        when "001"  => y <= "00000010";
        when "010"  => y <= "00000100";
        when "011"  => y <= "00001000";
        when "100"  => y <= "00010000";
        when "101"  => y <= "00100000";
        when "110"  => y <= "01000000";
        when "111"  => y <= "10000000";
        when others => y <= (others => '0');
      end case;
    end if;
  end process;
end architecture behavioral;
```

The code was analysed and simulated with GHDL; for all 8 input values the correct one-hot output appears, and with en = 0 all outputs are 0.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What is VHDL used for in embedded systems?
   A. Compiling C for the 8051
   B. Describing hardware for FPGAs/ASICs, custom peripherals and simulation
   C. Only drawing flowcharts
   D. Replacing the crystal
   Answer: B. VHDL describes digital hardware as text for custom processors, FPGAs/CPLDs and simulation. (Key point: Uses of VHDL)

2. For a 3-to-8 decoder with enable, what is the output when en = 1 and a = 101?
   A. 00100000
   B. 00000101
   C. 10100000
   D. 00000100
   Answer: A. Exactly one output is high; a = 5 selects y5, giving 00100000. (Key point: Decoder behaviour)

3. What happens to the outputs when en = 0?
   A. All outputs are 1
   B. All outputs are 0
   C. y0 is high
   D. Outputs hold their last value
   Answer: B. The default assignment sets all outputs low and only en = 1 enables a decode. (Key point: Disabled decoder)

4. Why is the process sensitive to en and a?
   A. It is combinational, so it must re-evaluate whenever an input changes
   B. It needs a clock
   C. To make a flip-flop
   D. To save power
   Answer: A. A combinational process must run when any of its inputs change. (Key point: Process sensitivity)

## Related in Embedded System

- [Design metrics of embedded system](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Adesign-metrics-embedded) — Embedded System, chapter 1, asked 3×
- [VHDL architectures; elevator controller](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-architectures-elevator) — Embedded System, chapter 9
- [GCD processor algorithm and VHDL](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-gcd-processor) — Embedded System, chapter 9, asked 3×
- [LCM processor algorithm and VHDL](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-lcm-processor) — Embedded System, chapter 9, asked 2×
- [VHDL entity, architecture; D flip-flop](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-entity-architecture-dff) — Embedded System, chapter 9
- [VHDL dataflow/behavioural models; JK flip-flop](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-dataflow-behavioural-jk) — Embedded System, chapter 9

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