---
title: "Programmed I/O disadvantages; DMA"
subject: "Operating System"
chapter: 6
key: "semester_6/operating_system:programmed-io-disadvantages-dma"
source: https://www.bctengineer.com/q/semester_6/operating_system/programmed-io-disadvantages-dma
site: BCT Engineering
---

# Programmed I/O disadvantages; DMA

Operating System · Chapter 6: I/O Management and Disk Scheduling

- Asked in: year not given
- Video: [Modes of Transfer | Programmed IO | Interrupt initiated IO |DMA](https://www.youtube.com/watch?v=nIbTBTKnrTo) — COMPUTER SCIENCE HUB
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/operating_system/programmed-io-disadvantages-dma
- Whole chapter: https://www.bctengineer.com/md/semester_6/operating_system/chapter-6

## Question

What are the disadvantages of programmed I/O? Explain about DMA.

## Short answer

Programmed I/O wastes CPU time polling and transferring each byte, reducing throughput and preventing computation overlap. DMA uses a controller to transfer blocks directly between memory and device, interrupting only when done, offloading the CPU.

## Answer

#### Programmed I/O (PIO)
In programmed I/O the CPU itself does all the data transfer. It polls the device status again and again (busy waiting) until the device is ready, then moves one byte/word at a time between memory and the device register.

**Disadvantages of programmed I/O**
- The CPU is kept busy in a polling loop, so CPU time is wasted, since devices are slow compared with the CPU.
- No other process can use the CPU during the transfer, so system throughput falls.
- The CPU must handle every byte, so large transfers are slow.
- Computation cannot overlap with I/O.
- It is poor for devices that supply data at unpredictable times.

#### Direct Memory Access (DMA)
DMA lets special hardware, the **DMA controller**, transfer a whole block of data between memory and a device directly, without the CPU handling each byte. The CPU only starts the transfer and receives one interrupt at the end.

```text
 CPU <----> Memory <----> Device ctrl
  |           ^  |            ^
  |           |  +--- bus ----+
  +--> DMA controller (address, count, control regs)
```

**Steps of a DMA read**
1. The CPU programs the DMA controller with the memory address, byte count, direction and device, and then carries on with other work.
2. The DMA controller asks the disk controller to transfer the data it has read into its buffer.
3. The disk controller transfers the data over the bus to the given memory address.
4. The DMA address register is incremented and the count decremented after each transfer.
5. When the count reaches zero, the DMA controller interrupts the CPU to say that the transfer is complete.

**Modes:** *cycle stealing* (one word at a time; the controller steals a bus cycle from the CPU) and *burst mode* (the controller holds the bus and transfers a whole block).

| Point | Programmed I/O | DMA |
|---|---|---|
| CPU involvement | During the whole transfer | Only at start and end |
| Speed for big blocks | Slow | Fast |
| Interrupts | None (the CPU polls) | One per block |
| Hardware | Simple | Needs a DMA controller |

DMA is therefore the best choice for fast devices like disks.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What is the main drawback of programmed I/O?
   A. It needs a DMA controller
   B. The CPU busy-waits polling the device, wasting CPU time
   C. It interrupts after every block only
   D. It cannot transfer any data
   Answer: B. Devices are slow, so polling keeps the CPU busy without useful work. (Key point: PIO main drawback)

2. What does the CPU do in a DMA transfer?
   A. Programs the DMA controller and gets one interrupt at the end
   B. Moves each byte itself
   C. Polls the device status repeatedly
   D. Waits with no other work
   Answer: A. The DMA controller moves the block; the CPU can do other work meanwhile. (Key point: DMA CPU role)

3. After each transfer in a DMA read, what happens?
   A. Count is incremented and address reset
   B. CPU is interrupted
   C. Address register is incremented and count decremented
   D. The bus is released permanently
   Answer: C. When count reaches zero, the controller interrupts the CPU. (Key point: DMA registers)

4. Which describes cycle stealing?
   A. DMA holds the bus for a whole block
   B. CPU transfers data while DMA waits
   C. Data bypasses memory
   D. DMA transfers one word at a time, stealing a bus cycle from the CPU
   Answer: D. Burst mode takes the bus for the whole block; cycle stealing takes one cycle at a time. (Key point: DMA modes)

## Related in Operating System

- [Programmed I/O, DMA, device-independent software](https://www.bctengineer.com/question.md?key=semester_6%2Foperating_system%3Aprogrammed-io-dma-device-independent) — Operating System, chapter 6

## Related in other subjects

- [Programmed vs interrupt-driven vs DMA](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aio-techniques-compare) — Computer Organization and Architecture, chapter 7, asked 5×
- [DMA vs programmed and interrupt-driven I/O](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adma-overcomes) — Computer Organization and Architecture, chapter 7, asked 3×