--- title: "Power MOSFET switching; threshold gate voltage" subject: "Power Electronics" chapter: 1 key: "semester_7/power_electronics:mosfet-switching-threshold" source: https://www.bctengineer.com/q/semester_7/power_electronics/mosfet-switching-threshold site: BCT Engineering --- # Power MOSFET switching; threshold gate voltage Power Electronics · Chapter 1: Characteristics and specification of power electronic devices - Asked in: 2071 Shrawan, 8 marks - Video: [Power Electronics WK3_2 MOSFET Turn On Characteristics](https://www.youtube.com/watch?v=f1yt0s3gpcE) — Power Electronics with Dr. K - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_7/power_electronics/mosfet-switching-threshold - Whole chapter: https://www.bctengineer.com/md/semester_7/power_electronics/chapter-1 ## Question Describe the switching characteristics of power MOSFET. What is meant by threshold gate voltage? ## Short answer Turn-on has delay td(on) while Cgs charges to VGS(th), then rise time tr as iD grows and vDS falls; turn-off has delay td(off) and fall time tf. No storage time. The threshold voltage VGS(th) is the minimum gate-source voltage to form an inversion layer and start drain current, typically 2–4 V; above that iD = K(VGS−VGS(th))². ## Answer A **power MOSFET** is a voltage-controlled, majority-carrier switch. Its switching characteristics show how the drain current responds when the gate-source voltage is switched ON and OFF; the delays come from charging and discharging the gate capacitances $C_{gs}$ and $C_{gd}$. ```text D | | |--+ G --| | n-channel | |--+ power MOSFET | (body diode D->S S not shown) ``` #### Switching characteristics ```text vGS ^ _______________ | VGS | | | VT +-. | . |----' ` | `------- iD ^ ____________ | /| |\ |--------' | | `------ ||tr| ||tf| ``` - **Turn-on delay $t_{d(on)}$:** time to charge the input capacitance ($C_{gs}$) from zero to the threshold voltage $V_{GS(th)}$; no drain current flows yet. - **Rise time $t_r$:** gate voltage rises from $V_{GS(th)}$ to the value $V_{GSP}$ needed to carry full drain current; $i_D$ rises to its full value and $v_{DS}$ falls (Miller plateau while $C_{gd}$ charges). - **Turn-off delay $t_{d(off)}$:** when the gate drive is removed, the input capacitance discharges from $V_{GS}$ down to $V_{GSP}$; $i_D$ is still full. - **Fall time $t_f$:** gate voltage falls from $V_{GSP}$ to $V_{GS(th)}$; drain current falls to zero. $t_{on} = t_{d(on)} + t_r$ and $t_{off} = t_{d(off)} + t_f$. Because the MOSFET is a majority carrier device there is **no storage time**, so it switches in tens of nanoseconds; the switching speed depends only on how fast the driver can charge and discharge the gate capacitances. #### Threshold gate voltage The **threshold gate voltage** $V_{GS(th)}$ (or $V_T$) is the minimum gate-source voltage at which an inversion layer (channel) forms under the gate, so drain current starts to flow. - For $V_{GS} < V_{GS(th)}$ the MOSFET is OFF (only leakage current). - For $V_{GS} > V_{GS(th)}$ the drain current in saturation is $i_D = K(V_{GS} - V_{GS(th)})^2$. - Typical power MOSFETs have $V_{GS(th)} = 2$ to 4 V and are driven fully ON with $V_{GS} = 10$ to 15 V to get low $R_{DS(on)}$. - $V_{GS(th)}$ falls with temperature, so noise immunity is lower when hot; a negative off-bias is sometimes used. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. During the turn-on delay time t_d(on) of a power MOSFET: A. The drain current rises to its full value B. The input capacitance charges from zero to the threshold voltage and no drain current flows C. The Miller plateau occurs D. Minority carrier storage is removed Answer: B. t_d(on) is the time to charge Cgs up to V_GS(th); only after that does drain current begin. (Key point: Turn-on delay) 2. Why does a power MOSFET switch in tens of nanoseconds with no storage time? A. It is a minority carrier device with high gain B. It has a very large gate capacitance C. It is a majority carrier device, so speed depends only on charging and discharging the gate capacitances D. It uses a negative gate bias at all times Answer: C. No minority carriers are stored, so only gate capacitance charging limits the speed. (Key point: Reason for fast switching) 3. What is the threshold gate voltage V_GS(th)? A. The gate voltage at which the device is fully ON with minimum R_DS(on) B. The maximum gate voltage the oxide can withstand C. The drain-source voltage at which breakdown occurs D. The minimum gate-source voltage at which an inversion channel forms and drain current starts to flow Answer: D. Below V_GS(th) the MOSFET is OFF; above it a channel forms under the gate. (Key point: Threshold gate voltage) 4. In turn-off, what happens during the fall time t_f? A. Gate voltage falls from V_GSP to V_GS(th) and drain current falls to zero B. Gate voltage falls from V_GS to V_GSP while drain current stays full C. Gate voltage rises to V_GSP D. The body diode starts conducting the load current Answer: A. The delay t_d(off) covers V_GS dropping to V_GSP with i_D still full; t_f is the drop to threshold with i_D going to zero. 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