--- title: "Step-up cycloconverter, four times frequency" subject: "Power Electronics" chapter: 6 key: "semester_7/power_electronics:step-up-cyclo-four-times" source: https://www.bctengineer.com/q/semester_7/power_electronics/step-up-cyclo-four-times site: BCT Engineering --- # Step-up cycloconverter, four times frequency Power Electronics · Chapter 6: AC voltage controller - Asked in: 2081 Bhadra, 5 marks - Video: [Step Up Cycloconverter (Basics, Circuit, Modes, Working, Waveforms & Applications) Explained](https://www.youtube.com/watch?v=d65OinQbRVg) — Engineering Funda - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_7/power_electronics/step-up-cyclo-four-times - Whole chapter: https://www.bctengineer.com/md/semester_7/power_electronics/chapter-6 ## Question Explain the operation of the step-up cyclo-converter for stepping up frequency to four times of fundamental frequency. ## Short answer For output frequency four times input, each input half cycle is divided into four intervals, alternating positive and negative group SCRs. Forced commutation is required because SCRs must turn off before natural zero. Output consists of slices of input sine wave. ## Answer A step-up cycloconverter gives an output frequency higher than the input ($f_o = n f_i$). Since each thyristor must be turned off in the middle of a supply half cycle, while it is still forward biased (before its natural current zero), **forced commutation** is needed. Mid-point circuit: ```text a o----+---P1->|---+ | +---|<-N1---+ ~ vs Tr| | (input) O o----[ Load ]----+ (common point K) | | b o----+---P2->|---+ +---|<-N2---+ ``` - In the positive input half cycle ($a$ positive): P1 gives a positive load voltage $+v_{aO}$; N2 gives a negative load voltage. - In the negative input half cycle ($b$ positive): P2 gives a positive load voltage; N1 gives a negative load voltage. #### Operation for $f_o = 4f_i$ (50 Hz to 200 Hz) Each input half cycle (10 ms) must contain 4 output half cycles, i.e. two full output cycles. So each input half cycle is divided into 4 equal intervals of 2.5 ms: | Input half | Interval | SCR ON | Output | |---|---|---|---| | + | 1 | P1 | + | | + | 2 | N2 | − | | + | 3 | P1 | + | | + | 4 | N2 | − | | − | 5 | P2 | + | | − | 6 | N1 | − | | − | 7 | P2 | + | | − | 8 | N1 | − | At the end of each interval, the conducting SCR is turned off by a forced-commutation circuit and the next one is fired. ```text vs _____ / \ ---/-------\---------/-- \_______/ vo _ _ _ _ | | | | | | | | ---+-+-+-+----+-+-+-+--- |_| |_| |_| |_| P1 N2 P1 N2 P2 N1 P2 N1 ``` The output consists of slices of the input sine wave with alternating sign; its fundamental is 200 Hz. The output amplitude follows the input envelope, so the harmonic content is high. Step-up cycloconverters are used less often than step-down types; typical uses are induction heating and high-speed drives. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Why does a step-up cycloconverter need forced commutation? A. Thyristors must turn off before the supply current reaches zero B. The supply frequency is too low C. The load is capacitive only D. The transformer saturates Answer: A. Output switching occurs within an input half cycle, so natural current zeros are not available at the switching instants. (Key point: Commutation need) 2. For fo = 4 fi (50 Hz to 200 Hz), how is each input half cycle (10 ms) divided? A. Into 2 intervals of 5 ms B. Into 4 equal intervals of 2.5 ms C. Into 8 intervals of 1.25 ms D. Into 3 intervals of 3.3 ms Answer: B. Each input half cycle contains 4 output half cycles, i.e. two full output cycles. (Key point: Interval division) 3. Which SCR sequence applies in the positive input half cycle? A. P1 P1 N2 N2 B. P1 N2 P2 N1 C. P1 P2 P1 P2 D. P1 N2 P1 N2 Answer: D. P1 gives positive output and N2 negative output, alternating each interval; P2 and N1 do the same in the negative input half. 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