--- title: "Levels of abstraction in computer simulation" subject: "Simulation and Modeling" chapter: 10 key: "semester_8/simulation_and_modeling:computer-system-abstraction-levels" source: https://www.bctengineer.com/q/semester_8/simulation_and_modeling/computer-system-abstraction-levels site: BCT Engineering --- # Levels of abstraction in computer simulation Simulation and Modeling · Chapter 10: Simulation of computer systems - Asked in: 2072 Ashwin, 6 marks - Video: [Level of Abstraction in Computer System // Simulation IOE Chapter10](https://www.youtube.com/watch?v=vBcUbV7WUfY) — Suyan Shrestha - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_8/simulation_and_modeling/computer-system-abstraction-levels - Whole chapter: https://www.bctengineer.com/md/semester_8/simulation_and_modeling/chapter-10 ## Question Explain the different level of abstraction for the simulation of computer system. ## Short answer Simulation abstraction levels range from circuit (transistors, accurate but slow) to workload (user jobs, fast but less detail). Intermediate levels include gate, register-transfer (RTL), instruction-set (ISA), and system (queuing model). Lower levels suit hardware design, higher levels suit performance analysis. ## Answer A computer system can be simulated at different **levels of abstraction**. A lower level shows more detail and is more accurate, but needs more data, effort and run time; a higher level hides detail and is faster. The level is selected by the purpose of the study. #### Levels (from low to high) | Level | What is modelled | Typical use | |---|---|---| | Circuit level | Transistors, voltages, currents | Chip design, timing of circuits | | Gate / logic level | Logic gates, flip-flops, signals | Digital logic verification | | Register-transfer level | Registers, ALU, buses, clock cycles | CPU design, control unit | | Instruction-set level | Instructions, registers, memory contents | Testing programs, compilers, ISA | | Component / system level | CPU, memory, disk, network as service centres | Performance of the whole system | | Workload / application level | Users, jobs, transactions, requests | Capacity planning, response time | #### Explanation 1. **Circuit and gate level**: deterministic, built with HDL and electrical simulators. Not discrete-event in the queueing sense. 2. **Register-transfer level**: models the data path cycle by cycle. 3. **Instruction level**: models execution of machine instructions without the hardware detail. 4. **System level**: uses queueing theory and discrete-event simulation. The CPU, memory and I/O devices are servers with queues; jobs are customers. 5. **Workload level**: describes how users generate load (arrival rate, think time, job mix), and may drive a system-level model. ```text detail, accuracy, run time high ^ Circuit | Gate | Register transfer | Instruction set | System (queues) | Workload low ``` #### Choosing the level - Use a **lower level** when the design of hardware is being checked. - Use a **higher level** to compare scheduling, caching or the number of servers. - Mixed models may use detail for the component of interest and abstraction for others. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How do lower and higher levels of abstraction compare? A. Lower levels are faster and need less data B. Lower levels show more detail and accuracy but need more data, effort and run time C. Higher levels are more accurate than lower levels D. Both need the same effort Answer: B. Lower levels model more detail, so they are more accurate but costlier; higher levels hide detail and run faster. (Key point: Detail vs speed trade-off) 2. Which list is ordered from lowest to highest level? A. Workload, system, instruction set, RTL, gate, circuit B. Circuit, gate, register-transfer, instruction set, system, workload C. Gate, circuit, instruction set, RTL, workload, system D. Circuit, register-transfer, gate, system, instruction set, workload Answer: B. The order from low to high is circuit, gate, RTL, instruction set, system (queues), workload. (Key point: Order of levels) 3. How is the system level modelled? A. CPU, memory and I/O devices are servers with queues and jobs are customers, using queueing theory and discrete-event simulation B. Using transistors and voltage equations C. By simulating each logic gate with HDL D. By tracing each instruction's register changes Answer: A. At system level the components are service centres with queues, simulated as discrete events. (Key point: System level modelling) 4. To compare scheduling policies, caching or the number of servers, which level should be used? A. Circuit level B. Gate level C. A higher level such as system level D. Always the lowest level for accuracy Answer: C. Performance comparisons use a higher level; lower levels are for checking hardware design. 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