---
title: "CPU simulation at lower abstraction level"
subject: "Simulation and Modeling"
chapter: 10
key: "semester_8/simulation_and_modeling:cpu-lower-level-abstraction"
source: https://www.bctengineer.com/q/semester_8/simulation_and_modeling/cpu-lower-level-abstraction
site: BCT Engineering
---

# CPU simulation at lower abstraction level

Simulation and Modeling · Chapter 10: Simulation of computer systems

- Asked in: 2073 Bhadra, 6 marks
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_8/simulation_and_modeling/cpu-lower-level-abstraction
- Whole chapter: https://www.bctengineer.com/md/semester_8/simulation_and_modeling/chapter-10

## Question

Explain about simulation of a central processing unit for the lower level of abstraction.

## Short answer

At lower abstraction, the CPU is simulated at instruction-set or register-transfer level, modelling registers, ALU, control unit, and fetch–decode–execute cycles. Each instruction updates state and consumes clock cycles, verifying design correctness, though slower than high‑level models.

## Answer

At the lower levels of abstraction, a central processing unit is simulated not as a queueing server but as a **hardware machine**, modelling its internal registers, buses and the way it executes instructions. The aim is to check a CPU design or to run programs on a machine that does not yet exist.

#### Levels (lower side)
1. **Instruction-set (functional) level**: models what each instruction does to registers and memory; timing is by instruction counts.
2. **Register-transfer level (RTL)**: models data moving between registers through the ALU on every clock cycle, controlled by the control unit.
3. **Gate / circuit level**: models logic gates and electrical behaviour (usually done with hardware description languages).

#### Elements modelled
- Registers: program counter (PC), instruction register (IR), accumulator, general registers, status flags.
- ALU operations, memory array, buses.
- Control unit: decodes opcode and generates micro-operations.
- Optional: pipeline stages, cache, interrupts.

#### Instruction cycle
```text
 +-------+   +--------+   +---------+
 | FETCH |-->| DECODE |-->| EXECUTE |--+
 +-------+   +--------+   +---------+  |
     ^                                  |
     +--------- update PC ---------------+
```
1. **Fetch**: IR = Memory[PC]; PC = PC + 1.
2. **Decode**: determine the opcode and operands.
3. **Execute**: perform the operation, update registers, flags and memory.
4. Add the clock cycles used to the simulated clock.

#### Example (simple simulator loop)
```text
while (not halted):
    IR = MEM[PC]; PC += 1
    op, addr = decode(IR)
    if op == LOAD:  ACC = MEM[addr]
    if op == ADD:   ACC = ACC + MEM[addr]
    if op == STORE: MEM[addr] = ACC
    if op == JMP:   PC = addr
    cycles += cost[op]
```
Running a small program shows the final register contents and the total cycles, so the design can be verified.

#### Remarks
Lower-level simulation is very accurate but slow and needs detailed knowledge; higher levels are faster and are used for performance studies. The level is chosen according to the question being asked.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. At lower levels of abstraction, how is the CPU simulated?
   A. As a queueing server with a service time
   B. As a hardware machine with registers, buses and instruction execution
   C. As a stream of user requests
   D. As a probability distribution of job sizes
   Answer: B. Lower-level simulation models internal registers, buses and how instructions execute, not a queueing server. (Key point: Hardware machine model)

2. What does the register-transfer level (RTL) model?
   A. Transistor voltages and currents
   B. Data moving between registers through the ALU on every clock cycle, directed by the control unit
   C. Only the count of instructions executed
   D. Users and job mix
   Answer: B. RTL models cycle-by-cycle register transfers through the ALU under control unit signals. (Key point: Register-transfer level)

3. What happens in the fetch step of the simulated instruction cycle?
   A. ACC = ACC + MEM[addr]
   B. IR = Memory[PC]; PC = PC + 1
   C. Opcode is decoded into operands
   D. Flags are updated after the operation
   Answer: B. Fetch loads the instruction at PC into IR and increments PC; decode and execute follow. (Key point: Instruction cycle)

4. In the simulator loop, why is cycles += cost[op] included, and what is the trade-off of low-level simulation?
   A. To count clock cycles used; it is very accurate but slow and needs detailed knowledge
   B. To count requests; it is fast and needs little detail
   C. To set the PC; it is inaccurate but easy
   D. To detect halts; it is only used for performance studies
   Answer: A. The simulated clock accumulates cycles per instruction; low-level simulation is accurate but slow and detail-hungry. (Key point: Cycle counting and trade-off)

## Related in Simulation and Modeling

- [Levels of abstraction in computer simulation](https://www.bctengineer.com/question.md?key=semester_8%2Fsimulation_and_modeling%3Acomputer-system-abstraction-levels) — Simulation and Modeling, chapter 10
- [CPU simulation with example](https://www.bctengineer.com/question.md?key=semester_8%2Fsimulation_and_modeling%3Acpu-simulation-example) — Simulation and Modeling, chapter 10, asked 4×
- [Simulation of computer system serving WWW](https://www.bctengineer.com/question.md?key=semester_8%2Fsimulation_and_modeling%3Acomputer-system-www-request) — Simulation and Modeling, chapter 10, asked 2×

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