---
title: "Memory simulation with example"
subject: "Simulation and Modeling"
chapter: 10
key: "semester_8/simulation_and_modeling:memory-simulation"
source: https://www.bctengineer.com/q/semester_8/simulation_and_modeling/memory-simulation
site: BCT Engineering
---

# Memory simulation with example

Simulation and Modeling · Chapter 10: Simulation of computer systems

- Asked in: 2074 Magh, 6 marks
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_8/simulation_and_modeling/memory-simulation
- Whole chapter: https://www.bctengineer.com/md/semester_8/simulation_and_modeling/chapter-10

## Question

Discuss memory simulation with example.

## Short answer

Trace-driven simulation feeds address traces to a memory model. For 3 frames and reference string 7,0,1,2,0,3,0,4,2,3,0,3,2, FIFO gave 3 hits (hit ratio 0.23), LRU gave 4 hits (0.31); using t_mem=100 ns, t_miss=8 ms, FIFO effective time ≈ 6.15 ms, LRU ≈ 5.54 ms.

## Answer

Memory simulation models the behaviour of a computer's memory system (main memory, cache or virtual memory) to estimate performance measures such as hit ratio, page-fault rate and average access time. It is usually **trace-driven**: a sequence of memory references (an address trace), taken from a real program or generated randomly, is fed to a model of the memory and its replacement policy.

#### Components
- Memory structure: page size, number of frames (or cache lines), associativity.
- Replacement policy: FIFO, LRU, optimal, random.
- Reference string (input): the order in which pages are referenced.
- Output: hits, misses (faults), hit ratio, effective access time = h × t_mem + (1 - h) × t_miss.

#### Algorithm
1. Read the next page reference.
2. If the page is already in a frame, count a hit (and update the usage order for LRU).
3. Otherwise, count a fault; if all frames are full, remove a page according to the policy; then load the page.
4. Repeat until the end of the string and report the statistics.

```text
reference -> [in memory?] -yes-> hit
                  |no
             [free frame?] -no-> replace (FIFO/LRU)
                  |
              load page -> fault count + 1
```

#### Example: 3 frames
Reference string: 7, 0, 1, 2, 0, 3, 0, 4, 2, 3, 0, 3, 2 (13 references).

**FIFO**

| Ref | 7 | 0 | 1 | 2 | 0 | 3 | 0 | 4 | 2 | 3 | 0 | 3 | 2 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Frames | 7 | 7,0 | 7,0,1 | 0,1,2 | 0,1,2 | 1,2,3 | 2,3,0 | 3,0,4 | 0,4,2 | 4,2,3 | 2,3,0 | 2,3,0 | 2,3,0 |
| Result | F | F | F | F | H | F | F | F | F | F | F | H | H |

FIFO: 3 hits, 10 faults; hit ratio = 3/13 = 0.23.

**LRU** gives faults at 7, 0, 1, 2, 3, 4, 2, 3, 0, i.e. 9 faults and 4 hits (the 0 at position 5, the 0 at position 7, and the final 3 and 2); hit ratio = 4/13 = 0.31. So LRU performs better for this string.

With t_mem = 100 ns and t_miss = 8 ms, even a small difference in hit ratio changes the effective access time greatly: FIFO gives about (3/13)(100 ns) + (10/13)(8 ms) ≈ 6.15 ms, while LRU gives about (4/13)(100 ns) + (9/13)(8 ms) ≈ 5.54 ms. The simulation lets the designer choose the number of frames and the replacement policy; cache simulation follows the same method, using block addresses and mapping rules.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What is the input to a typical memory simulation?
   A. A sequence of memory references (address trace or reference string) fed to a model of memory and replacement policy
   B. The disk service time only
   C. A random circuit netlist
   D. The CPU clock frequency only
   Answer: A. Memory simulation is trace-driven: the reference string is run through the memory and replacement model. (Key point: Trace-driven simulation)

2. On a page fault when all frames are full, what does the algorithm do?
   A. Counts a hit and continues
   B. Removes a page by the replacement policy, loads the new page and counts a fault
   C. Ignores the reference
   D. Doubles the number of frames
   Answer: B. A fault with full frames causes eviction by the policy (FIFO/LRU), loading of the page and a fault count increase. (Key point: Algorithm on a fault)

3. Which formula gives effective access time with hit ratio h?
   A. h × t_miss + (1 - h) × t_mem
   B. h × t_mem + (1 - h) × t_miss
   C. h + t_mem + t_miss
   D. t_mem / h
   Answer: B. Hits cost t_mem and misses cost t_miss, so EAT = h × t_mem + (1 - h) × t_miss. (Key point: Effective access time)

4. For the 13-reference string with 3 frames, which result is correct?
   A. FIFO 3 hits, 10 faults; LRU 4 hits, 9 faults, so LRU is better
   B. FIFO 4 hits, LRU 3 hits
   C. Both have 10 faults
   D. LRU has 13 faults
   Answer: A. FIFO gives hit ratio 3/13 = 0.23 and LRU 4/13 = 0.31, so LRU performs better for this string. (Key point: Example result)