--- title: "TSI in random read, sequential write mode" subject: "Telecommunications" chapter: 4 key: "semester_8/telecommunications:tsi-random-read-sequential-write" source: https://www.bctengineer.com/q/semester_8/telecommunications/tsi-random-read-sequential-write site: BCT Engineering --- # TSI in random read, sequential write mode Telecommunications · Chapter 4: Digital Switching - Asked in: 2081 Baisakh, 8 marks - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_8/telecommunications/tsi-random-read-sequential-write - Whole chapter: https://www.bctengineer.com/md/semester_8/telecommunications/chapter-4 ## Question Describe the working principle of TSI or Time switch in random read, sequential write mode. ## Short answer In sequential-write random-read mode, incoming samples are written into speech memory sequentially by a time-slot counter. A control memory stores the input slot address for each output slot; during readout, the control memory value addresses the speech memory, swapping the sample to the desired output slot, with a delay up to one frame (125 µs). ## Answer A **time switch** or **Time Slot Interchanger (TSI)** moves the speech sample (PCM byte) in one time slot of an incoming TDM frame into a different time slot of the outgoing frame. In **sequential write, random read** mode (also called *output-associated control*), samples are written into memory in order and read out in the order set by a control memory. #### Main parts - **Speech (data) memory, SM:** $c$ locations, one per time slot, each 8 bits wide (one PCM sample). For a 32-channel PCM frame, $c = 32$. - **Control (connection) memory, CM:** $c$ locations, each holding an SM address ($\log_2 c$ bits, 5 bits for 32 slots). - **Time-slot counter:** a modulo-$c$ counter driven by the channel clock. It gives the current slot number $0, 1, \dots, c-1$. - **Write/read control logic** and the processor interface that loads the CM when a call is set up. ```text Input TDM Output TDM frame frame ----->+---------------------+---------> | Speech memory | | (c x 8 bits) | +---------------------+ write addr ^ ^ read addr (sequential) | | (random) +-------------+ +------------+ | Time-slot |->| Control | | counter | | memory | +-------------+ +------------+ ^ processor (call set-up) ``` #### Working principle 1. **Write phase (sequential):** in time slot $i$ of the incoming frame, the sample is written into SM location $i$. The write address comes straight from the time-slot counter, so SM fills in order 0, 1, 2, ... every frame. 2. **Read phase (random):** in output time slot $j$, the counter addresses CM location $j$. CM($j$) contains the SM address of the input slot that must go out in slot $j$. That SM location is read and placed in output slot $j$. 3. When a call is set up, the processor writes the input slot number into the CM location of the wanted output slot. When the call is released, the entry is cleared. 4. Each slot needs one write and one read, so in every slot time the memory is accessed twice. #### Example Connect input TS3 to output TS7 (32-slot frame): - In TS3 the sample is written into SM(3). - The processor has stored CM(7) = 3. - In TS7 the logic reads CM(7) = 3, then reads SM(3) and sends it in output slot 7. - The sample is delayed by $7 - 3 = 4$ slots. If the output slot comes before the input slot, the sample goes out in the next frame (delay up to one frame, 125 µs). #### Timing limit Frame time is 125 µs, so slot time is $125/c$ µs. Since there are two accesses per slot, the memory cycle time must satisfy $$ t_{access} \le \frac{125\ \mu s}{2c} $$ For $c = 32$: $t_{access} \le 1.95$ µs. Faster memory allows more channels per TSI. #### Features - Strictly non-blocking: any input slot can go to any free output slot. - Gives a fixed delay of less than one frame per stage. - Size is limited by memory speed, so large exchanges combine T stages with S stages (TST). - Broadcasting is easy: several CM locations can hold the same SM address, so one input can feed several outputs. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. In sequential write, random read mode, where does the write address come from? A. The control memory B. The time-slot counter C. The processor directly D. The output slot's CM entry Answer: B. The sample of input slot i is written into SM(i), with the address taken from the modulo-c time-slot counter. (Key point: Write addressing) 2. To connect input TS3 to output TS7, what does the processor store? A. CM(3) = 7 B. CM(7) = 3 C. SM(3) = 7 D. CM(7) = 7 Answer: B. The CM is indexed by the output slot and holds the SM address to read, so CM(7) = 3. (Key point: Role of control memory) 3. Why must the memory access time satisfy t <= 125 µs / (2c)? A. Two accesses (one write, one read) occur in each slot time B. The frame has 2c bits C. There are two control memories D. The counter runs at twice the clock Answer: A. Slot time is 125/c µs and each slot needs a write and a read, so each access gets at most 125/(2c) µs (1.95 µs for c = 32). (Key point: Memory access time) 4. Why is broadcasting easy in this mode? A. Several CM locations can hold the same SM address B. The SM has several write ports C. The counter repeats samples D. Each output has its own SM Answer: A. Several output slots can read the same SM location, so one input feeds many outputs. (Key point: Broadcast) ## Close variants set in other exams - [TSI in sequential read, random write mode](https://www.bctengineer.com/question.md?key=semester_8%2Ftelecommunications%3Atsi-sequential-read-random-write) — Telecommunications, chapter 4, asked 2× ## Related in Telecommunications - [Compare TSI write/read modes](https://www.bctengineer.com/question.md?key=semester_8%2Ftelecommunications%3Atsi-write-read-modes-compare) — Telecommunications, chapter 4