---
title: "TSI in sequential read, random write mode"
subject: "Telecommunications"
chapter: 4
key: "semester_8/telecommunications:tsi-sequential-read-random-write"
source: https://www.bctengineer.com/q/semester_8/telecommunications/tsi-sequential-read-random-write
site: BCT Engineering
---

# TSI in sequential read, random write mode

Telecommunications · Chapter 4: Digital Switching

- Asked in: 2076 Chaitra, 8 marks
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_8/telecommunications/tsi-sequential-read-random-write
- Whole chapter: https://www.bctengineer.com/md/semester_8/telecommunications/chapter-4

## Question

Describe the working principle of TSI switch in sequential read, random write mode.

## Short answer

In sequential read, random write mode, the control memory CM(i) gives the speech memory address j for input slot i, so the sample is written randomly. The speech memory is then read sequentially, so SM(j) leaves in output slot j. Delay is less than one frame, and broadcast is not possible.

## Answer

A **time switch** or **TSI (Time Slot Interchanger)** changes the time slot of a PCM sample within a TDM frame. In the **sequential read, random write** mode (also called *input-associated control*), the address at which each incoming sample is written is chosen by a control memory, and the speech memory is read out in order.

#### Main parts
- **Speech memory (SM):** $c$ words of 8 bits, one per time slot.
- **Control memory (CM):** $c$ words of $\log_2 c$ bits. CM($i$) holds the SM address where the sample of input slot $i$ must be written.
- **Time-slot counter:** a modulo-$c$ counter giving the current slot number.
- **Processor interface:** loads CM entries when calls are set up or released.

```text
 Input TDM                              Output TDM
 --------->+---------------------+---------->
           |   Speech memory     |
           |   (c x 8 bits)      |
           +---------------------+
  write addr ^             ^ read addr
   (random)  |             | (sequential)
      +------------+  +-------------+
      | Control    |<-| Time-slot   |
      | memory     |  | counter     |
      +------------+  +-------------+
           ^
   processor (call set-up)
```

#### Working principle
1. **Write phase (random):** in input slot $i$, the counter addresses CM($i$). The value stored there, say $j$, is used as the write address, so the sample is stored in SM($j$).
2. **Read phase (sequential):** the counter also gives the read address directly. In output slot $j$, SM($j$) is read and sent out. So a sample written into SM($j$) leaves in output slot $j$.
3. To set up a call from input slot $i$ to output slot $j$, the processor writes $j$ into CM($i$).
4. One write and one read happen in every slot.

#### Example
Connect input TS2 to output TS9 in a 32-slot frame:
- Processor sets CM(2) = 9.
- In TS2 the sample is written into SM(9).
- In TS9 the counter reads SM(9), so the sample appears in output slot 9.
- Delay = $9 - 2 = 7$ slots $= 7 \times 3.9 \approx 27.3$ µs.

#### Timing
Slot time = $125/c$ µs and two memory accesses per slot are needed:
$$
t_{access} \le \frac{125\ \mu s}{2c}
$$
For 32 channels this is 1.95 µs. Maximum channels for a memory of access time $t$: $c_{max} = 125\ \mu s / 2t$.

#### Features
- Strictly non-blocking for its own frame.
- Delay is less than one frame (125 µs).
- **Broadcast is not possible** in this mode, because one input sample is written into only one SM location. (In sequential-write, random-read mode, several outputs can read the same location.)
- Commonly used for the output time stage of a TST switch: there the TSI's input slot is the internal slot $x$, so its control memory is addressed by the same slot number as the space-stage control memory.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. In sequential read, random write mode, the write address comes from
   A. The time-slot counter
   B. CM(i), the control memory entry for the input slot
   C. The output slot number
   D. A random number generator
   Answer: B. CM(i) holds the SM address j where the sample of input slot i is written. (Key point: Write address source)

2. To connect input TS2 to output TS9, the processor sets
   A. CM(9) = 2
   B. CM(2) = 9
   C. SM(2) = 9
   D. CM(2) = 2
   Answer: B. The CM is indexed by the input slot and holds the output slot: sample goes to SM(9) and is read sequentially in slot 9. (Key point: Call set-up)

3. Why is broadcasting not possible in this mode?
   A. One input sample is written into only one SM location
   B. The SM is read twice
   C. The CM is too small
   D. The counter is sequential
   Answer: A. Each input slot has one CM entry, so its sample is stored in a single location and leaves in a single output slot. (Key point: No broadcast)

4. The delay for input TS2 to output TS9 with 3.9 µs slots is about
   A. 7 x 3.9 = 27.3 µs
   B. 9 x 3.9 = 35 µs
   C. 125 µs
   D. 2 x 3.9 = 7.8 µs
   Answer: A. Delay = (9 - 2) slots = 7 slots, about 27.3 µs. (Key point: Delay)

## Close variants set in other exams

- [TSI in random read, sequential write mode](https://www.bctengineer.com/question.md?key=semester_8%2Ftelecommunications%3Atsi-random-read-sequential-write) — Telecommunications, chapter 4, asked 2×

## Related in Telecommunications

- [Compare TSI write/read modes](https://www.bctengineer.com/question.md?key=semester_8%2Ftelecommunications%3Atsi-write-read-modes-compare) — Telecommunications, chapter 4