---
title: "Compare TSI write/read modes"
subject: "Telecommunications"
chapter: 4
key: "semester_8/telecommunications:tsi-write-read-modes-compare"
source: https://www.bctengineer.com/q/semester_8/telecommunications/tsi-write-read-modes-compare
site: BCT Engineering
---

# Compare TSI write/read modes

Telecommunications · Chapter 4: Digital Switching

- Asked in: 2076 Asoj, 5 marks
- Video: [Lecture - 9 Time Switching types with switching map examples in Time Division Switching Networks.](https://www.youtube.com/watch?v=YzNdjMDmvf8) — Engineering Jnana
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_8/telecommunications/tsi-write-read-modes-compare
- Whole chapter: https://www.bctengineer.com/md/semester_8/telecommunications/chapter-4

## Question

In the case of a Time Slot Interchanger (TSI), compare the working mechanisms between Sequential Write and Random Read with Random Write and Sequential Read.

## Short answer

Sequential write, random read uses the counter for writing and CM indexed by output slot for reading, so broadcast is possible. Random write, sequential read uses CM indexed by input slot for writing and the counter for reading, so broadcast is not possible. Both need the same memory size and are non-blocking for one frame.

## Answer

A TSI has a **speech memory (SM)** holding one PCM sample per time slot and a **control memory (CM)** set by the processor. The two modes differ in which access (write or read) the CM controls.

#### Sequential write, random read (output-associated control)
- Input sample in slot $i$ is written into SM($i$), using the time-slot counter as address.
- In output slot $j$, CM($j$) gives the SM address to read; the sample of that input slot is sent out.
- To connect input $i$ to output $j$: set **CM($j$) = $i$**.

#### Random write, sequential read (input-associated control)
- In input slot $i$, CM($i$) gives the SM address $j$ where the sample is written.
- SM is read in order, so SM($j$) goes out in output slot $j$.
- To connect input $i$ to output $j$: set **CM($i$) = $j$**.

```text
 SW-RR:  in --> SM[counter]      SM[CM[counter]] --> out
 RW-SR:  in --> SM[CM[counter]]  SM[counter]     --> out
```

**Example:** input TS4 to output TS10. SW-RR: sample stored in SM(4), CM(10) = 4. RW-SR: CM(4) = 10, sample stored in SM(10). Output is the same in both.

| Point | Sequential write, random read | Random write, sequential read |
|---|---|---|
| Write address | From time-slot counter | From control memory |
| Read address | From control memory | From time-slot counter |
| CM indexed by | Output slot | Input slot |
| Control type | Output-associated | Input-associated |
| Broadcast (one input to many outputs) | Possible | Not possible |
| Common use in TST | Input time stage | Output time stage |
| Delay | Less than one frame | Less than one frame |
| Memory speed needed | $t \le 125/2c$ µs | Same |

Both modes need the same memory size ($c \times 8$ bits SM, $c \times \log_2 c$ bits CM) and are non-blocking for one frame. They are often used together in a TST switch (SW-RR at the input stage, RW-SR at the output stage), because then the control memories of all three stages are addressed by the same internal slot number $x$.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. In sequential write, random read mode, the control memory is indexed by
   A. Input slot
   B. Output slot
   C. Frame number
   D. Highway number
   Answer: B. CM(j) gives the SM address to read in output slot j; in the other mode it is indexed by the input slot. (Key point: CM indexing)

2. To connect input TS4 to output TS10 in random write, sequential read mode:
   A. CM(10) = 4
   B. CM(4) = 10
   C. CM(4) = 4
   D. CM(10) = 10
   Answer: B. Input-associated control: CM(i) = j, so CM(4) = 10 and the sample is stored in SM(10). (Key point: Connecting 4 to 10)

3. Which mode permits broadcasting?
   A. Sequential write, random read
   B. Random write, sequential read
   C. Both
   D. Neither
   Answer: A. In random-read mode several CM entries can point to the same SM location. (Key point: Broadcast)

4. Which is the same for both modes?
   A. Memory size and the t <= 125/(2c) µs access requirement
   B. Which memory the counter addresses
   C. Whether broadcast works
   D. Whether the CM is indexed by input
   Answer: A. Both use c x 8 bit SM, c x log2 c bit CM and need two accesses per slot. (Key point: Common features)

## Related in Telecommunications

- [TSI in random read, sequential write mode](https://www.bctengineer.com/question.md?key=semester_8%2Ftelecommunications%3Atsi-random-read-sequential-write) — Telecommunications, chapter 4, asked 2×
- [TSI in sequential read, random write mode](https://www.bctengineer.com/question.md?key=semester_8%2Ftelecommunications%3Atsi-sequential-read-random-write) — Telecommunications, chapter 4, asked 2×
- [TDM frame, time slot and 24-channel system](https://www.bctengineer.com/question.md?key=semester_8%2Ftelecommunications%3Atdm-frame-24-channel) — Telecommunications, chapter 3