Short note: PLA

A PLA (Programmable Logic Array) is a programmable logic device made of a programmable AND array followed by a programmable OR array. It implements several Boolean functions in sum-of-products (SOP) form.

Structure (n inputs, k product terms, m outputs):

inputs --[buffers: true and complement]
            |
   [ programmable AND array ] -> P1 ... Pk
            |
   [ programmable OR array ]  -> F1 ... Fm
            |
   [ XOR / inverter (optional) ] -> outputs

• Each input is given in true and complemented form.
• Each AND gate forms one product term by connecting chosen literals.
• Each OR gate adds any chosen product terms. A product term can be shared by several outputs.
• Size is given as $n \times k \times m$, e.g. a 3 × 4 × 2 PLA.

Design steps:

1. Simplify each function to minimum SOP (try both $F$ and $F'$ to reduce product terms).
2. Find the common product terms.
3. Write the PLA programming table (inputs used, output connections, true/complement).

Example: $F_1 = AB' + AC$, $F_2 = AC + BC$ need only three product terms ($AB'$, $AC$, $BC$) since $AC$ is shared.

Advantages: both arrays programmable, so very flexible; shares product terms; uses fewer terms than a PROM for functions with many inputs.

Disadvantages: two programmable arrays make it slower and costlier than a PAL; harder to manufacture.