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Log-antilog circuit: Vo in terms of Vi and VR

Short answer

The first op-amp with Q1 forms a log amplifier giving VE = -VT ln(Vi/(R1*Is)). Q2 with base voltage VR has IC2 = (Vi/R1) exp(VR/VT). The second op-amp converts this current: Vo = (R2/R1) Vi exp(VR/VT). Matching cancels Is, yielding a voltage-controlled exponential gain amplifier.

For the circuit shown in figure below, find the relationship between V0 and Vi (find the expression for V0 in terms of Vin and VR; Q1 and Q2 are matched transistors). [Figure: Input V through R1 to the inverting input of op-amp A1 (non-inverting input grounded). Transistor Q1 is the feedback element of A1: base grounded, collector at the inverting input, emitter at the A1 output. The A1 output drives the emitter of matched transistor Q2, whose base is connected to the reference voltage VR. The collector of Q2 goes to the inverting input of op-amp A2 (non-inverting input grounded), which has feedback resistor R2 from its output Vo to its inverting input.]

The first stage (A1 with Q1) is a log amplifier. Q2 with A2 is an antilog stage whose base is lifted by VR. The overall circuit multiplies Vi by an exponential function of VR, a voltage-controlled gain.

Circuit (as given)

                 Q1 (base GND)
          C +-----|<|-----+ E
 Vi-[R1]-+--(-)\         |
         GND-(+) A1>-----+---VE---+
                                  | E
                    VR ---- B --[Q2]
                                  | C        R2
                                  +----+---/\/\/--+
                                       |          |
                                     (-)\ A2      |
                                 GND-(+)  >-------+--> Vo

Assumptions

Q1 and Q2 are matched npn transistors (same Is). The op-amps are ideal, so both inverting inputs are at 0 V. The transistor law is:

IC = Is · exp(VBE / VT),   so   VBE = VT ln(IC / Is)

Stage 1 (log amplifier)

The current Vi/R1 flows into the collector of Q1 (collector at virtual ground, base grounded):

IC1 = Vi / R1
VBE1 = VB1 − VE = 0 − VE
VE = −VBE1 = −VT ln( Vi / (R1·Is) )

Stage 2 (antilog amplifier)

Q2 has its base at VR, its emitter at VE, and its collector at the virtual ground of A2:

VBE2 = VR − VE = VR + VT ln( Vi / (R1·Is) )

IC2 = Is · exp(VBE2 / VT)
    = Is · exp(VR/VT) · exp( ln( Vi/(R1·Is) ) )
    = Is · exp(VR/VT) · Vi / (R1·Is)
    = (Vi / R1) · exp(VR / VT)

The collector current IC2 is drawn from A2's inverting node. It is supplied through R2 from the output, so:

Vo = IC2 · R2

Result

Vo = (R2/R1) · Vi · exp(VR / VT)
  • Is cancels because the transistors are matched. The output does not depend on the strongly temperature-dependent saturation current.
  • With VR = 0, Vo = (R2/R1)Vi, a plain linear amplifier.
  • The gain changes exponentially with VR: every 60 mV of VR (at 300 K, VT ≈ 26 mV) multiplies the gain by about 10. So the circuit is a voltage-controlled exponential gain amplifier.
  • VT = kT/q still appears, so a temperature-compensating resistor is needed in the VR path for accuracy.

✓ Answer checked by Claude Opus 5.5 (high effort)

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