Short note: Programmable Interrupt Controller

A Programmable Interrupt Controller (PIC) is a support chip that manages interrupt requests from several I/O devices and presents them to the processor through its single interrupt input. The standard chip for 8085 and 8086 systems is the Intel 8259A.

Main features of the 8259A

• Handles 8 interrupt requests (IR0–IR7); up to 64 using one master and 8 slaves (cascading).
• Resolves priority: fixed priority, rotating priority, or special mask mode, programmable by software.
• Each input can be masked individually.
• For the 8086 it supplies the 8-bit interrupt type number on the data bus; for the 8085 it supplies a 3-byte CALL instruction (CDH followed by the ISR address).
• Edge-triggered or level-triggered inputs.
• Programmed with initialisation command words (ICW1–ICW4) and operation command words (OCW1–OCW3).

Internal blocks

 IR0..IR7 --> [IRR] -> [Priority] -> [ISR]
                |        resolver      |
              [IMR]                     v
                                  Control logic -> INT
 INTA' ---> Control logic        D7-D0 <-> data buffer
 CS', RD', WR', A0 -> read/write logic
 CAS0-2, SP/EN -> cascade buffer

• IRR: holds the pending requests. IMR: holds the mask bits. ISR: shows the request in service.
• Priority resolver: selects the highest-priority request.

Working (8086)

A device raises IRn. The 8259A sets the IRR bit and, if the request is unmasked and has the highest priority, sends INT to the CPU. When the CPU replies with INTA' pulses, the 8259A places the type number on the data bus and sets the ISR bit. The ISR ends with an EOI command.