Design goals of digital modulation; coherent BPSK

Design goals of digital modulation

A good digital modulation scheme aims to:

1. Maximise data rate for the available channel.
2. Minimise probability of symbol/bit error for a given $E_b/N_0$.
3. Minimise transmitted power (important for battery and satellite systems).
4. Minimise channel bandwidth (high spectral efficiency, bits/s/Hz).
5. Maximise resistance to interference and fading.
6. Minimise circuit complexity and cost.

These goals conflict (e.g. higher-level schemes save bandwidth but need more power), so the choice is a trade-off.

Coherent binary PSK

In BPSK the carrier phase is shifted by $180^\circ$ between the two symbols:

$$s_1(t)=\sqrt{\frac{2E_b}{T_b}}\cos 2\pi f_ct\ \ (\text{symbol }1),\qquad s_2(t)=-\sqrt{\frac{2E_b}{T_b}}\cos 2\pi f_ct\ \ (\text{symbol }0)$$

for $0\le t\le T_b$, where $E_b$ is the bit energy and $f_c=n_c/T_b$. The two signals are antipodal.

Signal space diagram

Only one orthonormal basis function is required:

$$\phi_1(t)=\sqrt{\frac{2}{T_b}}\cos 2\pi f_ct,\quad 0\le t\le T_b$$

so $s_1(t)=\sqrt{E_b}\,\phi_1(t)$ and $s_2(t)=-\sqrt{E_b}\,\phi_1(t)$. The coordinates are

$$s_{11}=\int_0^{T_b}s_1(t)\phi_1(t)dt=+\sqrt{E_b},\qquad s_{21}=-\sqrt{E_b}$$

        Z2 (decide 0)  |  Z1 (decide 1)
   s2                   |                   s1
 ---*-------------------+-------------------*---> phi1
 -sqrt(Eb)              0              +sqrt(Eb)
                 decision boundary

Distance $d_{12}=2\sqrt{E_b}$. The decision boundary is the midpoint, $x_1=0$.

Modulator

 binary data -->[Polar NRZ level encoder]--> b(t)
                 1 -> +sqrt(Eb), 0 -> -sqrt(Eb)
                                    |
                                   (X)<-- phi1(t)
                                    |
                                 BPSK s(t)

The level encoder converts 1 and 0 to $+\sqrt{E_b}$ and $-\sqrt{E_b}$; the product modulator multiplies by $\phi_1(t)$. The result is a constant-envelope carrier whose phase flips with the data.

Demodulator (coherent detector)

 x(t) -->(X)-->[ integral 0..Tb ]--x1--> [Decision device]
          ^                              x1 > 0 -> 1
        phi1(t)                          x1 < 0 -> 0
   (from carrier and bit-timing recovery)

1. The received signal $x(t)=s_i(t)+w(t)$ is multiplied by a locally generated $\phi_1(t)$, exactly in phase with the transmitted carrier.
2. The integrator over one bit gives $x_1=\pm\sqrt{E_b}+n$, where $n$ is Gaussian with variance $N_0/2$.
3. The decision device compares $x_1$ with zero.

Performance

$$P_e=\frac12\,\text{erfc}\left(\sqrt{\frac{E_b}{N_0}}\right)$$

BPSK has the lowest error probability of all binary schemes (3 dB better than coherent BFSK). Its null-to-null bandwidth is $2/T_b$. Its drawback is the need for an accurate coherent reference (Costas or squaring loop).