For 2^(k+1) x n from 2^k x n modules, what is done?

Two modules with the extra address bit A_k selecting one

One module with doubled data lines

Modules in series with no select

In the 2^k x 4n memory, how are the modules connected?

Share address, CS and R/W; each gives n bits of the word; no decoder

Each has own address; decoder selects one

2073 Bhadra · 4+4 marks

Construct 2^(k+1) x n and 2^k x 4n

Short answer

(a) Depth expansion for 2^(k+1)×n: two 2^k×n modules, A_k selects module via decoder. (b) Width expansion for 2^k×4n: four 2^k×n modules in parallel share address/control lines; each provides n bits to form 4n-bit word.

Construct 2^(k+1) × n and 2^k × 4n memories using 2^k × n memory modules.

Let the base module be 2^k x n (k address lines, n data lines, enable/chip-select CS, read/write).

(a) 2^(k+1) x n: double the depth (2 modules)

The word width is the same (n) but twice the words are needed, so the address has k + 1 bits.

Two modules, M0 and M1, receive address lines A(k-1)..A0 in parallel.
The extra high-order address bit A_k selects the module through a 1-to-2 decoder (A_k itself goes to CS of M1 and its inverse to CS of M0).
Data lines D(n-1)..D0 of both modules are tied together (tri-state outputs, only the enabled one drives the bus).

 A(k-1)..A0 ------------+------------+
                        |            |
 A_k --+--[NOT]--> CS [ M0 ]    CS [ M1 ] <-- A_k
                       2^k x n    2^k x n
                          \          /
                      D(n-1)..D0 (shared)

A_k	Module	Addresses
0	M0	0 to 2^k - 1
1	M1	2^k to 2^(k+1) - 1

(b) 2^k x 4n: increase the width by 4 (4 modules)

The number of words is the same (2^k) but each word must be 4n bits, so four modules are placed side by side.

All four modules share address lines A(k-1)..A0, CS and read/write lines.
Each module supplies n bits: M0 gives D(n-1)..D0, M1 gives D(2n-1)..Dn, M2 gives D(3n-1)..D2n, M3 gives D(4n-1)..D3n.
No decoder is needed.

 A(k-1)..A0, CS, R/W ----+--------+--------+--------+
                        [M0]     [M1]     [M2]     [M3]
                          |        |        |        |
                     D(n-1)..0  D(2n-1)..n D(3n-1)..2n D(4n-1)..3n
                         \-------- 4n-bit data bus --------/

✓ Answer checked by Claude Opus 5.5 (high effort)

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Construct 2^(k+1) x n and 2^k x 4n

(a) 2^(k+1) x n: double the depth (2 modules)

(b) 2^k x 4n: increase the width by 4 (4 modules)

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