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Control unit sub-operations of GPP
Short answer
The control unit executes the instruction cycle: fetch (IR←Mem[PC], PC++), decode, operand fetch, execute (ALU operation), and store result. For ADD R1, [2000H], it fetches the instruction, reads memory address 2000H, adds to R1, and writes back. Pipelining overlaps these steps to raise throughput.
Explain the control unit sub-operations (basic operations carried out by the controller, with instruction cycles) of a general-purpose processor with a suitable example.
The control unit (controller) of a GPP repeatedly executes the instruction cycle, a sequence of sub-operations (micro-operations) that bring an instruction from memory and carry it out. The basic stages are fetch, decode, execute and store.
Sub-operations
- Fetch: read the instruction from memory.
- MAR <- PC (put the address on the bus)
- MDR <- Memory[MAR] (read)
- IR <- MDR; PC <- PC + 1
- Decode: the control unit decodes the opcode in IR, determining the operation, the operand locations (addressing mode) and the control signals needed.
- Fetch operands: read registers or memory (e.g. MAR <- address field; MDR <- Memory[MAR]).
- Execute: the ALU performs the operation (add, AND, compare, shift, branch condition test).
- Store result: write the result into a register or memory (or update PC for jumps).
+-------+ +--------+ +---------+ +-------+
-->| Fetch |-->| Decode |-->| Execute |-->| Store |--+
+-------+ +--------+ +---------+ +-------+ |
^ |
+---------------- next instruction -----------+
Example: ADD R1, [2000H] (R1 <- R1 + memory[2000H])
| Cycle | Micro-operation |
|---|---|
| Fetch | MAR <- PC; IR <- Mem[MAR]; PC <- PC + 1 |
| Decode | Control unit finds ADD with a direct memory operand |
| Operand fetch | MAR <- 2000H; MDR <- Mem[MAR] |
| Execute | ALU: R1 + MDR |
| Store | R1 <- ALU result; status flags updated |
Pipelined processors overlap these sub-operations for several instructions to raise throughput.
✓ Answer checked by Claude Opus 5.5 (high effort)
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