- Asked 2/15
- 2075 Baisakh · 6 marks
Voltage divider bias, DC load line, Q point (20 V)
Short answer
Thevenin base: VTH = 20×10/(20+10)=6.67V, RTH=6.67kΩ. IB = (6.67−0.7)/(6.67k+101×4k)≈14.53μA. IC=βIB=1.453mA, IE≈1.467mA. VCE=20−1.453×2−1.467×4=11.22V. Load line ends: IC(sat)=20/(2+4)=3.33mA, VCE(cut-off)=20V. Q point: IC≈1.45mA, VCE≈11.2V.
Draw the DC load line and determine the Q point of the voltage divider biased transistor circuit having VCC = 20 V, RC = 2 kΩ, R1 = 20 kΩ, R2 = 10 kΩ, RE = 4 kΩ, β = 100.
Given: VCC = 20 V, RC = 2 kΩ, R1 = 20 kΩ, R2 = 10 kΩ, RE = 4 kΩ, β = 100. Assume VBE = 0.7 V.
+20 V
| |
[R1] [RC]
20k 2k
| |C
+---B--| NPN
| |E
[R2] |
10k [RE] 4k
| |
GND GND
Thevenin equivalent of the base circuit
- VTH = VCC R2/(R1 + R2) = 20 × 10/30 = 6.67 V
- RTH = R1 ∥ R2 = (20 × 10)/30 = 6.67 kΩ
Base current
IB = (VTH − VBE)/(RTH + (β + 1) RE) = (6.67 − 0.7)/(6.67 k + 101 × 4 k) = 5.967/410.67 k = 14.53 µA
Collector and emitter currents
- IC = β IB = 100 × 14.53 µA = 1.453 mA
- IE = (β + 1) IB = 1.467 mA
Collector-emitter voltage
VCE = VCC − IC RC − IE RE = 20 − 1.453 × 2 − 1.467 × 4 = 20 − 2.906 − 5.870 = 11.22 V
DC load line
KVL: VCC = IC RC + VCE + IE RE ≈ IC (RC + RE) + VCE
- Saturation point (VCE = 0): IC(sat) = VCC/(RC + RE) = 20/6 k = 3.33 mA
- Cut-off point (IC = 0): VCE = VCC = 20 V
IC (mA)
3.33 |\
| \
1.45 | *Q
| \
+----\------ VCE (V)
11.2 20
Answer: Q point: IC = 1.45 mA, VCE = 11.2 V (IB = 14.5 µA). The load line joins (VCE = 0, IC = 3.33 mA) to (VCE = 20 V, IC = 0).
✓ Answer checked by Claude Opus 5.5 (high effort)
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