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Voltage divider bias design, 15 V and 1.5 mA

Short answer

Set VE = 1.5 V, VCE = 7.5 V, I2 = 10 IB. RE = 991 Ω, RC = 4 kΩ, R1 ≈ 85.3 kΩ, R2 ≈ 16.1 kΩ. With RE bypassed, Av = –gm RC = –240, Rin ≈ 1.6 kΩ.

Design voltage divider bias (common emitter configuration) to get ICQ = 1.5 mA. Assume power supply voltage VCC = 15 V and beta of transistor is 110.

Design guidelines used

  1. Emitter voltage VE ≈ VCC/10 (large enough for thermal/bias stability, small enough to save swing).
  2. Collector-emitter voltage VCE ≈ VCC/2, so the output can swing equally up and down (Q-point at the centre of the load line).
  3. Divider current I2 = 10 IB, much greater than IB, so the base voltage is fixed and the bias is independent of β.
  4. VB = VE + 0.7 V.

Design

IC  = 1.5 mA        IB = IC/β = 1.5 mA/110 = 13.6 µA
IE  = IC + IB = 1.514 mA
VE  = VCC/10 = 1.5 V     RE = VE/IE = 1.5/1.514 mA = 991 Ω
VCE = VCC/2  = 7.5 V
RC  = (VCC - VE - VCE)/IC = (15 - 1.5 - 7.5)/1.5 mA = 4 kΩ
VB  = VE + 0.7 = 2.2 V
I2  = 10 IB = 136.4 µA
R2  = VB/I2 = 2.2/136.4 µA = 16.1 kΩ
R1  = (VCC - VB)/(I2 + IB) = 12.8/150 µA = 85.3 kΩ

Use these values, or the nearest standard values (R1 ≈ 85.3 kΩ, R2 ≈ 16.1 kΩ, RE ≈ 991 Ω, RC ≈ 4 kΩ). The emitter resistor RE is bypassed by a large capacitor CE; C1 and C2 are the coupling capacitors.

Check and small-signal results (RE bypassed)

re  = VT/IE = 25 mV/1.514 mA = 16.5 Ω
rπ  = (β+1) re = β/gm = 1.83 kΩ        gm = IC/VT = 60 mA/V
R1 || R2 = 13.6 kΩ
Rin = R1 || R2 || rπ = 1.6 kΩ
Av  = -gm RC = -60 mA/V × 4 kΩ = -240

Ro ≈ RC = 4 kΩ.

Answer: R1 ≈ 85 kΩ, R2 ≈ 16 kΩ, RE ≈ 1 kΩ, RC = 4 kΩ for ICQ = 1.5 mA; Av ≈ -240, Rin ≈ 1.6 kΩ (RE bypassed). VCEQ = 7.5 V puts the Q-point at the middle of the load line.

✓ Answer checked by Claude Opus 5.5 (high effort)

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