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ASCII code and binary-to-Excess-3 converter

Short answer

ASCII is a 7-bit code for 128 characters. A BCD-to-excess-3 converter adds 3 (0011) to a 4-bit digit; simplified expressions: W=A+BC+BD, X=B'C+B'D+BC'D', Y=CD+C'D', Z=D'. It uses AND, OR, NOT gates.

Define an ASCII code. Design a binary to excess-3 code converter circuit using basic gates.

ASCII code

ASCII (American Standard Code for Information Interchange) is a 7-bit alphanumeric code that represents 128 characters: letters, digits, symbols and control characters. Example: 'A' = 65 = 100 0001, 'a' = 97 = 110 0001, '0' = 48 = 011 0000.

Binary (BCD) to Excess-3 code converter

Inputs: 4-bit binary/BCD digit ABCDABCD (AA = MSB), valid 0–9. Outputs: Excess-3 code WXYZWXYZ = input + 3. Inputs 10–15 never occur, so they are don't cares (X).

DecABCDWXYZ
000000011
100010100
200100101
300110110
401000111
501011000
601101001
701111010
810001011
910011100

K-map simplification

Minterms (don't cares d=10d = 10–1515):

  • W=∑m(5,6,7,8,9)+dW = \sum m(5,6,7,8,9) + d
  • X=∑m(1,2,3,4,9)+dX = \sum m(1,2,3,4,9) + d
  • Y=∑m(0,3,4,7,8)+dY = \sum m(0,3,4,7,8) + d
  • Z=∑m(0,2,4,6,8)+dZ = \sum m(0,2,4,6,8) + d

K-map for WW (rows ABAB, columns CDCD):

          CD
 AB     00  01  11  10
 00   |  0 | 0 | 0 | 0 |
 01   |  0 | 1 | 1 | 1 |
 11   |  X | X | X | X |
 10   |  1 | 1 | X | X |

Groups: AA (rows 11 and 10), BDBD, BCBC.

Simplified expressions:

W=A+BC+BDX=BˉC+BˉD+BCˉDˉY=CD+CˉDˉZ=Dˉ\begin{aligned} W &= A + BC + BD \\ X &= \bar B C + \bar B D + B\bar C\bar D \\ Y &= CD + \bar C\bar D \\ Z &= \bar D \end{aligned}

(Each equation can be checked against all ten rows of the truth table.)

Logic circuit (basic gates)

 A ----------------------------+
 B --+--[AND]-- BC ------------+--[OR]--- W
 C --+                         |
 B --+--[AND]-- BD ------------+
 D --+

 B'--+--[AND]-- B'C -----------+
 C --+                         |
 B'--+--[AND]-- B'D -----------+--[OR]--- X
 D --+                         |
 B --+                         |
 C'--+--[AND]-- BC'D' ---------+
 D'--+

 C --+--[AND]-- CD ------------+--[OR]--- Y
 D --+                         |
 C'--+--[AND]-- C'D' ----------+
 D'--+

 D ----[NOT]---------------------------- Z

NOT gates generate Bˉ\bar B, Cˉ\bar C and Dˉ\bar D; the Dˉ\bar D inverter also drives output Z directly. The circuit therefore uses 7 AND gates, 3 OR gates and 3 NOT gates.

✓ Answer checked by Claude Opus 5.5 (high effort)

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