5×32 decoder using 3×8 decoders

A 5×32 decoder has 5 inputs $A_4A_3A_2A_1A_0$ and 32 outputs $D_0$–$D_{31}$; exactly one output is active for each input code. A 3×8 decoder (e.g. 74138) has 3 inputs, 8 outputs and an enable input E. Since $32/8 = 4$, four 3×8 decoders are needed.

Design idea

• The three low bits $A_2A_1A_0$ go to the inputs of all four decoders in parallel.
• The two high bits $A_4A_3$ select which one decoder is enabled. This is done with two NOT gates and four AND gates (a 2×4 decoding of $A_4A_3$):

Circuit

A4 ──┬────────[NOT]── A4'
A3 ──┼──┬─────[NOT]── A3'
     │  │
  E0 = A4'·A3'  (AND)
  E1 = A4'·A3   (AND)
  E2 = A4 ·A3'  (AND)
  E3 = A4 ·A3   (AND)

A2 A1 A0 (common to all four decoders)
     │
     ├──>+-----------+
     │   | 3x8  DEC0 |── D0 ... D7
     │   +-----------+
     │       E ── E0
     ├──>+-----------+
     │   | 3x8  DEC1 |── D8 ... D15
     │   +-----------+
     │       E ── E1
     ├──>+-----------+
     │   | 3x8  DEC2 |── D16 ... D23
     │   +-----------+
     │       E ── E2
     └──>+-----------+
         | 3x8  DEC3 |── D24 ... D31
         +-----------+
             E ── E3

Operation

For an input $A_4A_3A_2A_1A_0$, only one enable is 1, so only one decoder works; the others keep all outputs inactive. Inside that decoder, $A_2A_1A_0$ selects one of its 8 outputs. Output number = $8 \times (A_4A_3)_{10} + (A_2A_1A_0)_{10}$.

Example: input 10110 (22): $A_4A_3 = 10$ enables DEC2 (outputs 16–23); $A_2A_1A_0 = 110 = 6$ selects its output 6, i.e. $D_{16+6} = D_{22}$.

(With 74138 chips, the enable can instead be done using its three enable pins $G_1, \overline{G_{2A}}, \overline{G_{2B}}$, but the AND-gate method above works with any 3×8 decoder having one active-high enable.)