JFET construction, curve and drain current equation

Construction (n-channel JFET)

A JFET has a thin bar of n-type semiconductor (the channel) with ohmic contacts at its two ends, the source (S) and the drain (D). Heavily doped p⁺ regions are formed on both sides of the bar and joined together to form the gate (G). In operation, the p–n junctions between the gate and the channel are reverse biased, so the gate takes essentially no current.

        D
        |
   +----+-----+
   | p+  n  p+|
G--+  channel +--G
   | p+  n  p+|
   +----+-----+
        |
        S

Working principle

1. With VGS = 0 and a small VDS, electrons flow from source to drain along the channel, and ID increases linearly with VDS (ohmic region).
2. When VGS is made negative, the gate junctions are further reverse biased and the depletion regions widen, narrowing the channel. The channel resistance rises and ID falls. The gate voltage therefore controls ID.
3. As VDS increases, the depletion region is widest near the drain (the reverse bias there is VDG). At VDS = VGS - VP (= VGS + |VP|), the pinch-off point, the channel almost closes near the drain and ID becomes constant (saturation region).
4. At VGS = VP (e.g. -4 V), the channel closes completely and ID = 0.

Characteristic curves

Drain characteristics:

 ID
IDSS|        _________  VGS = 0
    |     _-'_________  VGS = -1 V
    |    / _-'________  VGS = -2 V
    |   / /  ________   VGS = -3 V
    +--+----------------- VDS
     ohmic | saturation | breakdown

Regions: ohmic (small VDS), saturation (pinch-off) and breakdown (high VDS).

Transfer characteristic: ID versus VGS is a parabola running from IDSS at VGS = 0 to ID = 0 at VGS = VP.

Drain current equation (Shockley)

In the saturation region:

ID = IDSS (1 - VGS/VP)²        for VP ≤ VGS ≤ 0

IDSS is the saturation current at VGS = 0, and VP is the pinch-off voltage (negative for an n-channel JFET). The transconductance is gm = (2 IDSS/|VP|)(1 - VGS/VP). The condition for saturation is VDS ≥ VGS - VP.