JFET ID and VDS (VP -3.5 V, IDSS 10 mA), pinch-off check

The capacitors are open for dc, and C3 only bypasses RS for ac, so the dc analysis is that of a voltage-divider biased JFET.

Method: find the gate voltage, write VGS in terms of ID, combine this with Shockley's equation, solve the quadratic and reject the root that is not physically possible. The gate current is zero.

Given

VDD = 20 V, IDSS = 10 mA, VP = -3.5 V, RD = 2.2 kΩ, RS = 1.1 kΩ, R1 = 910 kΩ, R2 = 110 kΩ (in the formulas below, resistances are in kΩ)

Step 1: gate voltage and bias line

VG = VDD R2/(R1 + R2) = 20 × 110/(910 + 110) = 2.157 V
VGS = VG - ID RS = 2.157 - 1.1 ID      (ID in mA)

Step 2: Shockley equation

ID = IDSS (1 - VGS/VP)² = 10 [1 - (2.157 - 1.1 ID)/(-3.5)]²
   = 10 (1.6162 - 0.3143 ID)²

Expanding gives the quadratic:

0.9878 ID² - 11.1593 ID + 26.1225 = 0
ID = 7.986 mA   or   3.312 mA

Step 3: choose the valid root

The root 7.986 mA gives VGS = -6.63 V, which is outside the range VP ≤ VGS ≤ 0 (the channel would be cut off), so it is rejected.

ID  = 3.312 mA
VGS = 2.157 - 1.1 × 3.312 = -1.486 V
VDS = VDD - ID (RD + RS) = 20 - 3.312 × (2.2 + 1.1) = 9.072 V

Pinch-off (saturation) check

The JFET is in the pinch-off region if VDS > VGS - VP:

VGS - VP = -1.486 - (-3.5) = 2.014 V
VDS = 9.072 V  >  2.014 V

Yes, VDS is greater than VGS - VP, so the transistor operates in the pinch-off (saturation) region and the Shockley equation used is valid.

Answer: ID ≈ 3.31 mA, VGS ≈ -1.49 V, VDS ≈ 9.07 V.