JFET divider bias ID, VGS, VDS (VP -2 V)

Method: find the gate voltage, write VGS in terms of ID, combine this with Shockley's equation, solve the quadratic and reject the root that is not physically possible. The gate current is zero.

Given

VDD = 24 V, IDSS = 4 mA, VP = -2 V, RD = 0.91 kΩ, RS = 3 kΩ, R1 = 12 MΩ, R2 = 8.75 MΩ (in the formulas below, resistances are in kΩ)

Step 1: gate voltage and bias line

VG = VDD R2/(R1 + R2) = 24 × 8750/(12000 + 8750) = 10.120 V
VGS = VG - ID RS = 10.120 - 3 ID      (ID in mA)

Step 2: Shockley equation

ID = IDSS (1 - VGS/VP)² = 4 [1 - (10.120 - 3 ID)/(-2)]²
   = 4 (6.0602 - 1.5 ID)²

Expanding gives the quadratic:

9 ID² - 73.7229 ID + 146.9061 = 0
ID = 4.768 mA   or   3.423 mA

Step 3: choose the valid root

The root 4.768 mA gives VGS = -4.18 V, which is outside the range VP ≤ VGS ≤ 0 (the channel would be cut off), so it is rejected.

ID  = 3.423 mA
VGS = 10.120 - 3 × 3.423 = -0.150 V
VDS = VDD - ID (RD + RS) = 24 - 3.423 × (0.91 + 3) = 10.614 V

Answer: ID ≈ 3.42 mA, VGS ≈ -0.15 V, VDS ≈ 10.61 V.