MOSFET ID, VDS, region and small-signal circuit

Given: VDD = 10 V, R1 = R2 = 10 MΩ, RD = RS = 6 kΩ, Vt = 1 V, k = 0.5 mA/V² (ID = k (VGS − Vt)²).

1. ID and VDS

The gate current is zero:

VG = 10 × 10/20 = 5 V

VGS = VG − ID RS = 5 − 6 ID (mA, kΩ)

ID = 0.5 (5 − 6 ID − 1)² = 0.5 (4 − 6 ID)²

18 ID² − 25 ID + 8 = 0 → ID = 0.889 mA or 0.5 mA

For ID = 0.889 mA, VGS = 5 − 5.33 = −0.33 V < Vt, so the device would be off; this root is rejected.

ID = 0.5 mA, VGS = 5 − 3 = 2 V

VDS = VDD − ID (RD + RS) = 10 − 0.5 × 12 = 4 V

2. Region of operation

VGS − Vt = 2 − 1 = 1 V. VGS > Vt, so a channel exists, and VDS = 4 V > 1 V = VGS − Vt. Hence the MOSFET operates in the saturation (pinch-off) region.

3. Small-signal ac equivalent circuit

gm = 2k (VGS − Vt) = 2 × 0.5 × 1 = 1 mA/V = 1 mS

The gate draws no current, so the input sees only the gate bias resistance RG = R1 ∥ R2 = 5 MΩ. Channel-length modulation is ignored (ro = ∞). Assuming the source is bypassed by a capacitor (common-source stage):

 G o-----+                 +----------+-----o D
         |  +              |          |
       [RG]  vgs      gm·vgs (↓)    [RD]
       5 MΩ  -             |         6 kΩ
         |                 |          |
 S o-----+-----------------+----------+-----o S (ground)

In words: RG = 5 MΩ is connected between gate and source; between drain and source there is the current source gm·vgs = 1 mS × vgs (flowing from drain to source) in parallel with RD = 6 kΩ (and RL, if connected). The gate and drain are separate nodes.

Voltage gain: Av = −gm RD = −1 mS × 6 kΩ = −6 (or −gm (RD ∥ RL) with a load). If RS is not bypassed, RS appears in series with the source terminal and Av = −gm RD/(1 + gm RS) = −6/7 = −0.86.

Answer: ID = 0.5 mA, VDS = 4 V, saturation region, gm = 1 mS.