Cache organization

Cache organization describes how the cache is arranged and connected so that it can store blocks and find them quickly.

   CPU <----> +------------------------------+ <----> Main
              |        CACHE                 |        memory
   address -->| Controller (hit/miss logic)  |
              |  +--------+  +------------+  |
              |  | Tag    |  | Data       |  |
              |  | memory |  | memory     |  |
              |  |V|D|tag |  | block data |  |
              |  +---+----+  +------+-----+  |
              |      v              |        |
              |  Comparator ----> hit/miss   |
              +------------------------------+

• Data memory: stores blocks (lines) copied from main memory; one line holds several words.
• Tag memory: stores the tag (high-order address bits) of each line, plus a valid bit and a dirty bit (for write-back).
• Comparator: compares the address tag with the stored tag; a match with the valid bit set is a hit.
• Controller: controls the read/write, block fetch on a miss, replacement and write policy.
• Mapping: direct, associative or set associative decides where a block may be placed.
• Address split: Tag | Line (or Set) | Word; the word field selects a word in the line.

On a read hit the word goes to the CPU; on a read miss the whole block is fetched from main memory and the word is forwarded to the CPU.