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Data dependency problem in pipelining

Short answer

A data hazard (RAW) occurs when an instruction needs an operand not yet written by an earlier instruction. Solutions include hardware interlocking (stall), operand forwarding (bypassing) to supply data early, compiler scheduling of instructions, and register renaming to eliminate false dependencies.

Discuss in detail the data dependency problem that arises in pipelining along with its solution.

Data dependency (data hazard) occurs when an instruction needs the result of a previous instruction which is still in the pipeline and has not yet been written back. If the pipeline goes on, the later instruction would read an old value.

Example:

 I1: ADD R1, R2, R3     ; R1 = R2 + R3  (result in EX)
 I2: SUB R4, R1, R5     ; needs new R1 in operand fetch

Types: RAW (read after write, true dependency), WAR (write after read) and WAW (write after write), the last two arising when instructions complete out of order.

Effect: without correction, I2 reads the old R1 and gives a wrong result. The pipeline must stall or the value be supplied early, which reduces speedup.

Solutions

  1. Hardware interlock: a circuit detects the dependency and holds the later instruction (inserts a bubble) until the result is ready.
  2. Operand forwarding (bypassing): the ALU result is sent straight to the ALU input of the next instruction through extra paths and multiplexers, without waiting for the register write.
  3. Compiler (software) scheduling / delayed load: the compiler inserts NOP instructions or reorders independent instructions between the dependent ones.
  4. Register renaming to remove WAR and WAW dependencies.

✓ Answer checked by Claude Opus 5.5 (high effort)

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