I/O module functions and priority interrupt

Functions of an I/O module

1. Control and timing: coordinates the flow of data between the CPU, memory and device.
2. Processor communication: decodes commands, exchanges data and reports status to the CPU.
3. Device communication: sends commands to the device and reads its status.
4. Data buffering: holds data to match the slow device speed with the fast CPU.
5. Error detection: detects device or transmission errors (for example parity) and reports them.
6. Address decoding and conversion: identifies the addressed device and converts data format.

Need for priority interrupt

Many devices may request service at the same time, or a new request may arrive while another is being served. The system needs a rule to decide which one is served first. A priority interrupt system establishes this order: urgent and fast devices (for example a disk) are given a higher priority than slow ones (for example a keyboard), it identifies the interrupting device, and a higher-priority interrupt can interrupt a lower-priority service routine. It also allows masking of chosen interrupts.

Types of priority interrupt

1. Software polling (polling): on any interrupt, a single branch address starts a polling routine that tests each device's status flag in priority order. The first device found with its flag set is serviced. It is simple and needs little hardware, but it is slow because identifying the device takes a long time.
2. Daisy chaining (serial priority): all devices share one interrupt request line. The interrupt acknowledge signal passes through the devices in series, starting from the highest priority one. The first requesting device blocks the signal and puts its vector address on the data bus. Cheap, but a failure breaks the chain and low-priority devices may starve.
3. Parallel priority: each device has its own bit in an interrupt register and a bit in a mask register. A priority encoder gives the highest-priority unmasked request, generating a vector address. Fast and flexible (masking) but needs more hardware.

 Daisy chain:
 CPU INTACK -> [Dev1 PI/PO] -> [Dev2] -> [Dev3] -> ...
 Interrupt request line (common, wired OR) <- all devices

 Parallel priority:
 Dev0..Dev3 -> Interrupt reg & Mask reg -> Priority encoder
                                             -> vector (x y) -> CPU