Interrupt driven data transfer

In interrupt driven I/O, the peripheral informs the processor when it is ready by activating an interrupt request line. The processor works on its main program and transfers data only when interrupted, so no time is wasted in polling.

Sequence

1. Main program initialises the port, loads pointers/counter, and enables interrupts (EI).
2. The device becomes ready and sets INTR.
3. The CPU finishes the current instruction, checks the request (and mask), and sends INTA'.
4. The return address (PC) and flags are pushed on the stack; the PC is loaded with the ISR address (vector).
5. The ISR saves registers, reads or writes the byte (IN/OUT), updates pointer and counter, clears the request, restores registers, enables interrupts, and executes RET/IRET.
6. The main program continues from where it stopped.

Flowcharts

 Main program          Interrupt service routine
 +----------+          +-------------------+
 | Start    |          | Save registers    |
 +----+-----+          +---------+---------+
 +----v-----+          +---------v---------+
 | Initialise|         | Read/write data   |
 | port, EI  |         | via port          |
 +----+-----+          +---------+---------+
 +----v-----+          +---------v---------+
 | Do other |<- INTR   | Update pointer,   |
 | tasks    |  occurs  | counter           |
 +----+-----+          +---------+---------+
      |                +---------v---------+
      v                | Restore registers |
 (continue)            | EI, RET           |
                       +-------------------+

8085 skeleton

        MVI A,0BH ; SIM: enable RST 7.5
        SIM
        EI
LOOP:   ...       ; main work
        JMP LOOP
ISR:    PUSH PSW
        IN 80H    ; read data
        STA 2000H
        POP PSW
        EI
        RET

Advantage: efficient CPU use. Disadvantage: interrupt latency and overhead per byte, so not suitable for very fast block transfers (use DMA).