Interfacing 8-bit ADC using interrupt

In interrupt-driven ADC interfacing, the CPU starts the conversion and continues other work. When the ADC finishes it raises its EOC (end of conversion) output, which interrupts the 8085, and the interrupt service routine reads the result. This avoids waiting or polling during the conversion time (100 us for ADC0809).

Block diagram (ADC0809, I/O mapped at 80H)

 Analog inputs IN0-IN7
        |
 +--------------+  OUT 80H pulse (IOW' + decode) -> START and ALE
 |   ADC 0809   |  channel number on D0-D2 -> ADD A, B, C
 |              |  IN 80H (IOR' + decode)      -> OE
 |   D0-D7 out  |--------------------> AD0-AD7 (data bus of 8085)
 |   EOC -------|-------------------> RST 7.5 (8085 interrupt input)
 |   CLK <- 640 kHz (from CLK OUT divided)
 +--------------+   Vref+ = 5 V, Vref- = 0

RST 7.5 is edge triggered (rising edge) and has the vector 003CH. EOC goes high at the end of conversion and stays high until a new conversion starts. If it were connected to the level-sensitive RST 5.5, it would interrupt again and again after every EI. The rising edge on RST 7.5 is latched, so the CPU is interrupted only once per conversion.

Process flow

 MAIN                         ISR (vector 003CH)
 Set stack, enable RST 7.5     Save registers
 EI                            IN 80H  (OE = 1, read data)
 Clear flag                    Store data in memory
 Select channel, OUT 80H       Set flag
   (start conversion)          Restore registers
 Do other work / wait flag     EI, RET
 Use stored data

ALP

        ORG 003CH
        JMP ADCISR          ; RST 7.5 vector
        ORG 2000H
START:  LXI SP,27FFH
        MVI A,1BH           ; SIM: reset 7.5 latch, MSE=1, mask 6.5 and 5.5, enable 7.5
        SIM
        EI
        XRA A
        STA 2051H           ; clear flag
        MVI A,00H           ; channel 0
        OUT 80H             ; ALE and START: conversion begins
HERE:   LDA 2051H           ; flag set by ISR
        ORA A
        JZ HERE             ; main program can do other work here
        LDA 2050H           ; converted data available
        HLT

ADCISR: PUSH PSW
        IN 80H              ; read ADC output (OE active)
        STA 2050H           ; store result
        MVI A,01H
        STA 2051H           ; set flag
        POP PSW
        EI
        RET

Reading the converted value takes only a few microseconds, and the CPU is free during the whole conversion.