- 2075 Asoj · 8 marks
10-bit DAC triangular wave at 500 Hz
Short answer
A 10-bit DAC is interfaced via 8255 ports A and B (control word 80H). The triangular wave is generated by ramping up and down in 32 steps of 32 codes each, with loop delays giving a frequency of ~504 Hz. Vref = 5 V yields a peak near 5 V.
Interface a 10-bit DAC with 8255 PPI and 8085 CPU running at 2 MHz. Write an ALP to generate a triangular wave of frequency 500 Hz using the same interfacing circuit. The amplitude of the triangular wave should be +5V.
Assumptions and interfacing
The 10-bit DAC is of the AD7533 type (current output with an op-amp, Vref = 5 V so that full scale is about +5 V). The 8085 runs at 2 MHz (T = 0.5 us). The 8255 is I/O mapped at 80H-83H. The 10 data bits are: low 8 bits on port A, upper 2 bits on PB1 PB0 (port B).
8085 -- AD0-AD7, IOW', RESET, A0,A1, CS' -- 8255
8255 PA0-PA7 -------> DAC D7..D0
8255 PB0,PB1 -------> DAC D8, D9
DAC IOUT --> op-amp (current-to-voltage) --> Vout 0 to +5 V
Control word: ports A and B output, mode 0: 1000 0000 = 80H.
Timing
A frequency of 500 Hz means a period of 2 ms: a ramp up of 1 ms and a ramp down of 1 ms (2000 T-states each). The 8085 cannot write all 1024 codes in 1 ms (it needs about 1 us per code), so each ramp is made of 32 steps of 32 codes each (a step of 32 x 4.88 mV = 156 mV, small enough for a smooth triangle after a low-pass filter).
Loop timing (T-states): up loop per step = MOV A,L (4) + OUT (10) + MOV A,H (4) + OUT (10) + DAD D (10) + MOV A,H (4) + CPI (7) + NOP (4) + JNZ (10) = 63. Down loop per step = DAD D (10) + 2 x (MOV + OUT = 14) + MOV A,H (4) + ORA L (4) + NOP (4) + JNZ (10) = 60. Total: up about 32 x 63 - 3 = 2013; down about 32 x 60 - 3 = 1917. The two LXI D (10 each), LXI H (10) and JMP (10) add 40. Cycle = 2013 + 1917 + 40 = 3970 T = 1.985 ms, so the frequency is 504 Hz (about 500 Hz, error about 1%).
Program
MVI A,80H
OUT 83H ; ports A,B output
START: LXI H,0000H ; 10-bit value in HL
LXI D,0020H ; step +32
UP: MOV A,L
OUT 80H ; low 8 bits
MOV A,H
OUT 81H ; upper 2 bits
DAD D ; HL = HL + 32
MOV A,H
CPI 04H ; reached 1024 ?
NOP
JNZ UP
LXI D,FFE0H ; step -32
DOWN: DAD D ; HL = HL - 32
MOV A,L
OUT 80H
MOV A,H
OUT 81H
MOV A,H
ORA L ; HL = 0 ?
NOP
JNZ DOWN
JMP START
The peak code is 03E0H (992), which gives 992/1024 x 5 V = 4.84 V. Use Vref = 5.16 V (or add a final step of 03FFH) if the peak must be exactly 5 V. The output is a triangle from 0 to +5 V at about 500 Hz.
✓ Answer checked by Claude Sonnet 5.5
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