12-bit DAC with 8085

A 12-bit DAC (for example DAC1208 / AD7545) has 12 inputs, but the 8085 has an 8-bit data bus. The CPU writes the 12-bit word in two bytes into two input latches, and then transfers both to the DAC register in one operation, so the output changes only once and glitches are avoided.

DAC1208 arrangement

• First write: upper 8 bits (D11-D4) into the 8-bit input latch (BYTE1/BYTE2' = 1, WR1').
• Second write: lower 4 bits (D3-D0) into the 4-bit input latch (BYTE1/BYTE2' = 0). Data is left justified in D7-D4 of the bus.
• Third write: XFER' and WR2' pulse moves both latches into the 12-bit DAC register, which drives the converter.

Block diagram (I/O mapped, ports 80H-82H)

 8085                       DAC1208
 AD0-AD7 (D0-D7) -------->  DI4-DI11 (8-bit latch) & DI0-DI3 (4-bit)
 IOW' --------------------> WR1', WR2'
 Decoder (74LS138):
   port 80H (A0=0) -------> CS', BYTE1/BYTE2' = 1  (high byte)
   port 81H --------------> CS', BYTE1/BYTE2' = 0  (low nibble)
   port 82H --------------> XFER'  (transfer to DAC register)
 DAC IOUT1, IOUT2 -> op-amp (current to voltage) -> Vout
 Vref = 10 V:  1 LSB = 10 / 4096 = 2.44 mV

Output Vout = -Vref x (N / 4096) for a standard current-to-voltage amplifier.

Program (12-bit value in HL: H = D11-D4, L = D3-D0 in the upper nibble)

        MOV A,H
        OUT 80H         ; high 8 bits to latch 1
        MOV A,L
        OUT 81H         ; low 4 bits (D7-D4) to latch 2
        OUT 82H         ; transfer to DAC register
        RET

Example: for the 12-bit value 0ABCH, H = ABH (D11-D4) and L = C0H (D3-D0 in the upper nibble). With the two-level latching the analog output changes only once for each complete word.